// *****************************************************************************
// Copyright (C) 2017 Cambridge Silicon Radio plc http://www.csr.com
//
// Title      : Kalimba DSP Assembler File
// File name  : /home/aura/register_builds_for_sw/aura_d01_20170808/aura/d01/results/apps_sys/regs/asm/io_map.asm
// Creator    : GenKalimbaAsm.pm
// Timestamp  : Tue Aug  8 15:05:51 BST 2017
//
// This file was generated automatically. It is recommended not to edit it.
//
// *****************************************************************************
// -- Registers --
.CONST $USB2_ENDPOINT_SELECT                 0x60041240; // RW   6 bits
.CONST $_USB2_ENDPOINT_SELECT                $USB2_ENDPOINT_SELECT; // RW   6 bits
.CONST $BITSERIAL0_CONFIG                    0x60043000; // RW  16 bits
.CONST $_BITSERIAL0_CONFIG                   $BITSERIAL0_CONFIG; // RW  16 bits
.CONST $BITSERIAL0_CONFIG2                   0x60043004; // RW  15 bits
.CONST $_BITSERIAL0_CONFIG2                  $BITSERIAL0_CONFIG2; // RW  15 bits
.CONST $BITSERIAL0_CONFIG3                   0x60043008; // RW   5 bits
.CONST $_BITSERIAL0_CONFIG3                  $BITSERIAL0_CONFIG3; // RW   5 bits
.CONST $BITSERIAL0_WORD_CONFIG               0x6004300C; // RW  12 bits
.CONST $_BITSERIAL0_WORD_CONFIG              $BITSERIAL0_WORD_CONFIG; // RW  12 bits
.CONST $BITSERIAL0_CONFIG_SEL_TIME           0x60043010; // RW  16 bits
.CONST $_BITSERIAL0_CONFIG_SEL_TIME          $BITSERIAL0_CONFIG_SEL_TIME; // RW  16 bits
.CONST $BITSERIAL0_CONFIG_SEL_TIME2          0x60043014; // RW   4 bits
.CONST $_BITSERIAL0_CONFIG_SEL_TIME2         $BITSERIAL0_CONFIG_SEL_TIME2; // RW   4 bits
.CONST $BITSERIAL0_REMOTE_SUBSYSTEM_SSID     0x60043018; // RW   4 bits
.CONST $_BITSERIAL0_REMOTE_SUBSYSTEM_SSID    $BITSERIAL0_REMOTE_SUBSYSTEM_SSID; // RW   4 bits
.CONST $BITSERIAL0_CURATOR_SSID              0x6004301C; // RW   4 bits
.CONST $_BITSERIAL0_CURATOR_SSID             $BITSERIAL0_CURATOR_SSID; // RW   4 bits
.CONST $BITSERIAL0_SLAVE_WRITE_COUNT         0x60043020; //  R  16 bits
.CONST $_BITSERIAL0_SLAVE_WRITE_COUNT        $BITSERIAL0_SLAVE_WRITE_COUNT; //  R  16 bits
.CONST $BITSERIAL0_SLAVE_READ_COUNT          0x60043024; //  R  16 bits
.CONST $_BITSERIAL0_SLAVE_READ_COUNT         $BITSERIAL0_SLAVE_READ_COUNT; //  R  16 bits
.CONST $BITSERIAL0_SLAVE_UNDERFLOW_BYTE      0x60043028; // RW   8 bits
.CONST $_BITSERIAL0_SLAVE_UNDERFLOW_BYTE     $BITSERIAL0_SLAVE_UNDERFLOW_BYTE; // RW   8 bits
.CONST $BITSERIAL0_SLAVE_DATA_READY_BYTE     0x6004302C; // RW   8 bits
.CONST $_BITSERIAL0_SLAVE_DATA_READY_BYTE    $BITSERIAL0_SLAVE_DATA_READY_BYTE; // RW   8 bits
.CONST $BITSERIAL0_SLAVE_NUM_PROTOCOL_WORDS  0x60043030; // RW  16 bits
.CONST $_BITSERIAL0_SLAVE_NUM_PROTOCOL_WORDS $BITSERIAL0_SLAVE_NUM_PROTOCOL_WORDS; // RW  16 bits
.CONST $BITSERIAL0_SLAVE_READ_COMMAND_BYTE   0x60043034; // RW   8 bits
.CONST $_BITSERIAL0_SLAVE_READ_COMMAND_BYTE  $BITSERIAL0_SLAVE_READ_COMMAND_BYTE; // RW   8 bits
.CONST $BITSERIAL0_RX_BUFFER                 0x60043038; // RW  12 bits
.CONST $_BITSERIAL0_RX_BUFFER                $BITSERIAL0_RX_BUFFER; // RW  12 bits
.CONST $BITSERIAL0_RX_BUFFER2                0x6004303C; // RW  12 bits
.CONST $_BITSERIAL0_RX_BUFFER2               $BITSERIAL0_RX_BUFFER2; // RW  12 bits
.CONST $BITSERIAL0_TX_BUFFER                 0x60043040; // RW  12 bits
.CONST $_BITSERIAL0_TX_BUFFER                $BITSERIAL0_TX_BUFFER; // RW  12 bits
.CONST $BITSERIAL0_TX_BUFFER2                0x60043044; // RW  12 bits
.CONST $_BITSERIAL0_TX_BUFFER2               $BITSERIAL0_TX_BUFFER2; // RW  12 bits
.CONST $BITSERIAL0_TXRX_LENGTH               0x60043048; // RW  16 bits
.CONST $_BITSERIAL0_TXRX_LENGTH              $BITSERIAL0_TXRX_LENGTH; // RW  16 bits
.CONST $BITSERIAL0_TXRX_LENGTH2              0x6004304C; // RW  16 bits
.CONST $_BITSERIAL0_TXRX_LENGTH2             $BITSERIAL0_TXRX_LENGTH2; // RW  16 bits
.CONST $BITSERIAL0_STREAMING_THRESHOLD       0x60043050; // RW  16 bits
.CONST $_BITSERIAL0_STREAMING_THRESHOLD      $BITSERIAL0_STREAMING_THRESHOLD; // RW  16 bits
.CONST $BITSERIAL0_RWB                       0x60043054; // RW   2 bits
.CONST $_BITSERIAL0_RWB                      $BITSERIAL0_RWB; // RW   2 bits
.CONST $BITSERIAL0_SET_SEL_INACTIVE          0x60043058; // RW   1 bits
.CONST $_BITSERIAL0_SET_SEL_INACTIVE         $BITSERIAL0_SET_SEL_INACTIVE; // RW   1 bits
.CONST $BITSERIAL0_CLK_RATE_HI               0x6004305C; // RW  16 bits
.CONST $_BITSERIAL0_CLK_RATE_HI              $BITSERIAL0_CLK_RATE_HI; // RW  16 bits
.CONST $BITSERIAL0_I2C_ADDRESS               0x60043060; // RW  10 bits
.CONST $_BITSERIAL0_I2C_ADDRESS              $BITSERIAL0_I2C_ADDRESS; // RW  10 bits
.CONST $BITSERIAL0_CLK_RATE_LO               0x60043064; // RW  16 bits
.CONST $_BITSERIAL0_CLK_RATE_LO              $BITSERIAL0_CLK_RATE_LO; // RW  16 bits
.CONST $BITSERIAL0_CLK_SAMP_OFFSET           0x60043068; // RW  16 bits
.CONST $_BITSERIAL0_CLK_SAMP_OFFSET          $BITSERIAL0_CLK_SAMP_OFFSET; // RW  16 bits
.CONST $BITSERIAL0_I2C_ACKS                  0x6004306C; //  R  16 bits
.CONST $_BITSERIAL0_I2C_ACKS                 $BITSERIAL0_I2C_ACKS; //  R  16 bits
.CONST $BITSERIAL0_WORDS_SENT                0x60043070; //  R  16 bits
.CONST $_BITSERIAL0_WORDS_SENT               $BITSERIAL0_WORDS_SENT; //  R  16 bits
.CONST $BITSERIAL0_DEEP_SLEEP_ACTIVE         0x60043074; // RW   1 bits
.CONST $_BITSERIAL0_DEEP_SLEEP_ACTIVE        $BITSERIAL0_DEEP_SLEEP_ACTIVE; // RW   1 bits
.CONST $BITSERIAL0_DEGLITCH_EN               0x60043078; // RW   2 bits
.CONST $_BITSERIAL0_DEGLITCH_EN              $BITSERIAL0_DEGLITCH_EN; // RW   2 bits
.CONST $BITSERIAL0_CLK_CONTROL               0x6004307C; // RW  10 bits
.CONST $_BITSERIAL0_CLK_CONTROL              $BITSERIAL0_CLK_CONTROL; // RW  10 bits
.CONST $BITSERIAL0_INTERBYTE_SPACING         0x60043080; // RW  16 bits
.CONST $_BITSERIAL0_INTERBYTE_SPACING        $BITSERIAL0_INTERBYTE_SPACING; // RW  16 bits
.CONST $BITSERIAL0_ERROR_STATUS              0x60043084; //  R   9 bits
.CONST $_BITSERIAL0_ERROR_STATUS             $BITSERIAL0_ERROR_STATUS; //  R   9 bits
.CONST $BITSERIAL0_STATUS                    0x60043088; //  R  13 bits
.CONST $_BITSERIAL0_STATUS                   $BITSERIAL0_STATUS; //  R  13 bits
.CONST $BITSERIAL0_INTERRUPT_STATUS          0x6004308C; //  R  14 bits
.CONST $_BITSERIAL0_INTERRUPT_STATUS         $BITSERIAL0_INTERRUPT_STATUS; //  R  14 bits
.CONST $BITSERIAL0_INTERRUPT_EN              0x60043090; // RW  14 bits
.CONST $_BITSERIAL0_INTERRUPT_EN             $BITSERIAL0_INTERRUPT_EN; // RW  14 bits
.CONST $BITSERIAL0_INTERRUPT_CLEAR           0x60043094; // RW  14 bits
.CONST $_BITSERIAL0_INTERRUPT_CLEAR          $BITSERIAL0_INTERRUPT_CLEAR; // RW  14 bits
.CONST $BITSERIAL0_INTERRUPT_SOURCE          0x60043098; //  R  14 bits
.CONST $_BITSERIAL0_INTERRUPT_SOURCE         $BITSERIAL0_INTERRUPT_SOURCE; //  R  14 bits
.CONST $BITSERIAL0_INTERRUPT_SOURCE_CLEAR    0x6004309C; // RW  14 bits
.CONST $_BITSERIAL0_INTERRUPT_SOURCE_CLEAR   $BITSERIAL0_INTERRUPT_SOURCE_CLEAR; // RW  14 bits
.CONST $BITSERIAL0_DEBUG_SEL                 0x600430A0; // RW   9 bits
.CONST $_BITSERIAL0_DEBUG_SEL                $BITSERIAL0_DEBUG_SEL; // RW   9 bits
.CONST $BITSERIAL1_CONFIG                    0x60044000; // RW  16 bits
.CONST $_BITSERIAL1_CONFIG                   $BITSERIAL1_CONFIG; // RW  16 bits
.CONST $BITSERIAL1_CONFIG2                   0x60044004; // RW  15 bits
.CONST $_BITSERIAL1_CONFIG2                  $BITSERIAL1_CONFIG2; // RW  15 bits
.CONST $BITSERIAL1_CONFIG3                   0x60044008; // RW   5 bits
.CONST $_BITSERIAL1_CONFIG3                  $BITSERIAL1_CONFIG3; // RW   5 bits
.CONST $BITSERIAL1_WORD_CONFIG               0x6004400C; // RW  12 bits
.CONST $_BITSERIAL1_WORD_CONFIG              $BITSERIAL1_WORD_CONFIG; // RW  12 bits
.CONST $BITSERIAL1_CONFIG_SEL_TIME           0x60044010; // RW  16 bits
.CONST $_BITSERIAL1_CONFIG_SEL_TIME          $BITSERIAL1_CONFIG_SEL_TIME; // RW  16 bits
.CONST $BITSERIAL1_CONFIG_SEL_TIME2          0x60044014; // RW   4 bits
.CONST $_BITSERIAL1_CONFIG_SEL_TIME2         $BITSERIAL1_CONFIG_SEL_TIME2; // RW   4 bits
.CONST $BITSERIAL1_REMOTE_SUBSYSTEM_SSID     0x60044018; // RW   4 bits
.CONST $_BITSERIAL1_REMOTE_SUBSYSTEM_SSID    $BITSERIAL1_REMOTE_SUBSYSTEM_SSID; // RW   4 bits
.CONST $BITSERIAL1_CURATOR_SSID              0x6004401C; // RW   4 bits
.CONST $_BITSERIAL1_CURATOR_SSID             $BITSERIAL1_CURATOR_SSID; // RW   4 bits
.CONST $BITSERIAL1_SLAVE_WRITE_COUNT         0x60044020; //  R  16 bits
.CONST $_BITSERIAL1_SLAVE_WRITE_COUNT        $BITSERIAL1_SLAVE_WRITE_COUNT; //  R  16 bits
.CONST $BITSERIAL1_SLAVE_READ_COUNT          0x60044024; //  R  16 bits
.CONST $_BITSERIAL1_SLAVE_READ_COUNT         $BITSERIAL1_SLAVE_READ_COUNT; //  R  16 bits
.CONST $BITSERIAL1_SLAVE_UNDERFLOW_BYTE      0x60044028; // RW   8 bits
.CONST $_BITSERIAL1_SLAVE_UNDERFLOW_BYTE     $BITSERIAL1_SLAVE_UNDERFLOW_BYTE; // RW   8 bits
.CONST $BITSERIAL1_SLAVE_DATA_READY_BYTE     0x6004402C; // RW   8 bits
.CONST $_BITSERIAL1_SLAVE_DATA_READY_BYTE    $BITSERIAL1_SLAVE_DATA_READY_BYTE; // RW   8 bits
.CONST $BITSERIAL1_SLAVE_NUM_PROTOCOL_WORDS  0x60044030; // RW  16 bits
.CONST $_BITSERIAL1_SLAVE_NUM_PROTOCOL_WORDS $BITSERIAL1_SLAVE_NUM_PROTOCOL_WORDS; // RW  16 bits
.CONST $BITSERIAL1_SLAVE_READ_COMMAND_BYTE   0x60044034; // RW   8 bits
.CONST $_BITSERIAL1_SLAVE_READ_COMMAND_BYTE  $BITSERIAL1_SLAVE_READ_COMMAND_BYTE; // RW   8 bits
.CONST $BITSERIAL1_RX_BUFFER                 0x60044038; // RW  12 bits
.CONST $_BITSERIAL1_RX_BUFFER                $BITSERIAL1_RX_BUFFER; // RW  12 bits
.CONST $BITSERIAL1_RX_BUFFER2                0x6004403C; // RW  12 bits
.CONST $_BITSERIAL1_RX_BUFFER2               $BITSERIAL1_RX_BUFFER2; // RW  12 bits
.CONST $BITSERIAL1_TX_BUFFER                 0x60044040; // RW  12 bits
.CONST $_BITSERIAL1_TX_BUFFER                $BITSERIAL1_TX_BUFFER; // RW  12 bits
.CONST $BITSERIAL1_TX_BUFFER2                0x60044044; // RW  12 bits
.CONST $_BITSERIAL1_TX_BUFFER2               $BITSERIAL1_TX_BUFFER2; // RW  12 bits
.CONST $BITSERIAL1_TXRX_LENGTH               0x60044048; // RW  16 bits
.CONST $_BITSERIAL1_TXRX_LENGTH              $BITSERIAL1_TXRX_LENGTH; // RW  16 bits
.CONST $BITSERIAL1_TXRX_LENGTH2              0x6004404C; // RW  16 bits
.CONST $_BITSERIAL1_TXRX_LENGTH2             $BITSERIAL1_TXRX_LENGTH2; // RW  16 bits
.CONST $BITSERIAL1_STREAMING_THRESHOLD       0x60044050; // RW  16 bits
.CONST $_BITSERIAL1_STREAMING_THRESHOLD      $BITSERIAL1_STREAMING_THRESHOLD; // RW  16 bits
.CONST $BITSERIAL1_RWB                       0x60044054; // RW   2 bits
.CONST $_BITSERIAL1_RWB                      $BITSERIAL1_RWB; // RW   2 bits
.CONST $BITSERIAL1_SET_SEL_INACTIVE          0x60044058; // RW   1 bits
.CONST $_BITSERIAL1_SET_SEL_INACTIVE         $BITSERIAL1_SET_SEL_INACTIVE; // RW   1 bits
.CONST $BITSERIAL1_CLK_RATE_HI               0x6004405C; // RW  16 bits
.CONST $_BITSERIAL1_CLK_RATE_HI              $BITSERIAL1_CLK_RATE_HI; // RW  16 bits
.CONST $BITSERIAL1_I2C_ADDRESS               0x60044060; // RW  10 bits
.CONST $_BITSERIAL1_I2C_ADDRESS              $BITSERIAL1_I2C_ADDRESS; // RW  10 bits
.CONST $BITSERIAL1_CLK_RATE_LO               0x60044064; // RW  16 bits
.CONST $_BITSERIAL1_CLK_RATE_LO              $BITSERIAL1_CLK_RATE_LO; // RW  16 bits
.CONST $BITSERIAL1_CLK_SAMP_OFFSET           0x60044068; // RW  16 bits
.CONST $_BITSERIAL1_CLK_SAMP_OFFSET          $BITSERIAL1_CLK_SAMP_OFFSET; // RW  16 bits
.CONST $BITSERIAL1_I2C_ACKS                  0x6004406C; //  R  16 bits
.CONST $_BITSERIAL1_I2C_ACKS                 $BITSERIAL1_I2C_ACKS; //  R  16 bits
.CONST $BITSERIAL1_WORDS_SENT                0x60044070; //  R  16 bits
.CONST $_BITSERIAL1_WORDS_SENT               $BITSERIAL1_WORDS_SENT; //  R  16 bits
.CONST $BITSERIAL1_DEEP_SLEEP_ACTIVE         0x60044074; // RW   1 bits
.CONST $_BITSERIAL1_DEEP_SLEEP_ACTIVE        $BITSERIAL1_DEEP_SLEEP_ACTIVE; // RW   1 bits
.CONST $BITSERIAL1_DEGLITCH_EN               0x60044078; // RW   2 bits
.CONST $_BITSERIAL1_DEGLITCH_EN              $BITSERIAL1_DEGLITCH_EN; // RW   2 bits
.CONST $BITSERIAL1_CLK_CONTROL               0x6004407C; // RW  10 bits
.CONST $_BITSERIAL1_CLK_CONTROL              $BITSERIAL1_CLK_CONTROL; // RW  10 bits
.CONST $BITSERIAL1_INTERBYTE_SPACING         0x60044080; // RW  16 bits
.CONST $_BITSERIAL1_INTERBYTE_SPACING        $BITSERIAL1_INTERBYTE_SPACING; // RW  16 bits
.CONST $BITSERIAL1_ERROR_STATUS              0x60044084; //  R   9 bits
.CONST $_BITSERIAL1_ERROR_STATUS             $BITSERIAL1_ERROR_STATUS; //  R   9 bits
.CONST $BITSERIAL1_STATUS                    0x60044088; //  R  13 bits
.CONST $_BITSERIAL1_STATUS                   $BITSERIAL1_STATUS; //  R  13 bits
.CONST $BITSERIAL1_INTERRUPT_STATUS          0x6004408C; //  R  14 bits
.CONST $_BITSERIAL1_INTERRUPT_STATUS         $BITSERIAL1_INTERRUPT_STATUS; //  R  14 bits
.CONST $BITSERIAL1_INTERRUPT_EN              0x60044090; // RW  14 bits
.CONST $_BITSERIAL1_INTERRUPT_EN             $BITSERIAL1_INTERRUPT_EN; // RW  14 bits
.CONST $BITSERIAL1_INTERRUPT_CLEAR           0x60044094; // RW  14 bits
.CONST $_BITSERIAL1_INTERRUPT_CLEAR          $BITSERIAL1_INTERRUPT_CLEAR; // RW  14 bits
.CONST $BITSERIAL1_INTERRUPT_SOURCE          0x60044098; //  R  14 bits
.CONST $_BITSERIAL1_INTERRUPT_SOURCE         $BITSERIAL1_INTERRUPT_SOURCE; //  R  14 bits
.CONST $BITSERIAL1_INTERRUPT_SOURCE_CLEAR    0x6004409C; // RW  14 bits
.CONST $_BITSERIAL1_INTERRUPT_SOURCE_CLEAR   $BITSERIAL1_INTERRUPT_SOURCE_CLEAR; // RW  14 bits
.CONST $BITSERIAL1_DEBUG_SEL                 0x600440A0; // RW   9 bits
.CONST $_BITSERIAL1_DEBUG_SEL                $BITSERIAL1_DEBUG_SEL; // RW   9 bits
.CONST $HOST_SYS_CONFIG_ENABLES              0x6004D000; // RW   5 bits
.CONST $_HOST_SYS_CONFIG_ENABLES             $HOST_SYS_CONFIG_ENABLES; // RW   5 bits
.CONST $HOST_SYS_CONFIG_FORCE_CLK_ENABLES    0x6004D004; // RW   7 bits
.CONST $_HOST_SYS_CONFIG_FORCE_CLK_ENABLES   $HOST_SYS_CONFIG_FORCE_CLK_ENABLES; // RW   7 bits
.CONST $HOST_SYS_CONFIG_MASK_HW_CLK_REQS     0x6004D008; // RW   5 bits
.CONST $_HOST_SYS_CONFIG_MASK_HW_CLK_REQS    $HOST_SYS_CONFIG_MASK_HW_CLK_REQS; // RW   5 bits
.CONST $HOST_SYS_BUILD_OPTIONS               0x6004D00C; //  R   6 bits
.CONST $_HOST_SYS_BUILD_OPTIONS              $HOST_SYS_BUILD_OPTIONS; //  R   6 bits
.CONST $HOST_SYS_BITSERIAL_0_DATA_OUTPUT_PIO_CTRL 0x6004D010; // RW   7 bits
.CONST $_HOST_SYS_BITSERIAL_0_DATA_OUTPUT_PIO_CTRL $HOST_SYS_BITSERIAL_0_DATA_OUTPUT_PIO_CTRL; // RW   7 bits
.CONST $HOST_SYS_BITSERIAL_0_CLK_OUTPUT_PIO_CTRL 0x6004D014; // RW   7 bits
.CONST $_HOST_SYS_BITSERIAL_0_CLK_OUTPUT_PIO_CTRL $HOST_SYS_BITSERIAL_0_CLK_OUTPUT_PIO_CTRL; // RW   7 bits
.CONST $HOST_SYS_BITSERIAL_0_SEL_OUTPUT_PIO_CTRL 0x6004D018; // RW   7 bits
.CONST $_HOST_SYS_BITSERIAL_0_SEL_OUTPUT_PIO_CTRL $HOST_SYS_BITSERIAL_0_SEL_OUTPUT_PIO_CTRL; // RW   7 bits
.CONST $HOST_SYS_BITSERIAL_0_DATA_INPUT_PIO_CTRL 0x6004D01C; // RW   7 bits
.CONST $_HOST_SYS_BITSERIAL_0_DATA_INPUT_PIO_CTRL $HOST_SYS_BITSERIAL_0_DATA_INPUT_PIO_CTRL; // RW   7 bits
.CONST $HOST_SYS_BITSERIAL_0_CLK_INPUT_PIO_CTRL 0x6004D020; // RW   7 bits
.CONST $_HOST_SYS_BITSERIAL_0_CLK_INPUT_PIO_CTRL $HOST_SYS_BITSERIAL_0_CLK_INPUT_PIO_CTRL; // RW   7 bits
.CONST $HOST_SYS_BITSERIAL_0_SEL_INPUT_PIO_CTRL 0x6004D024; // RW   7 bits
.CONST $_HOST_SYS_BITSERIAL_0_SEL_INPUT_PIO_CTRL $HOST_SYS_BITSERIAL_0_SEL_INPUT_PIO_CTRL; // RW   7 bits
.CONST $HOST_SYS_BITSERIAL_1_DATA_OUTPUT_PIO_CTRL 0x6004D028; // RW   7 bits
.CONST $_HOST_SYS_BITSERIAL_1_DATA_OUTPUT_PIO_CTRL $HOST_SYS_BITSERIAL_1_DATA_OUTPUT_PIO_CTRL; // RW   7 bits
.CONST $HOST_SYS_BITSERIAL_1_CLK_OUTPUT_PIO_CTRL 0x6004D02C; // RW   7 bits
.CONST $_HOST_SYS_BITSERIAL_1_CLK_OUTPUT_PIO_CTRL $HOST_SYS_BITSERIAL_1_CLK_OUTPUT_PIO_CTRL; // RW   7 bits
.CONST $HOST_SYS_BITSERIAL_1_SEL_OUTPUT_PIO_CTRL 0x6004D030; // RW   7 bits
.CONST $_HOST_SYS_BITSERIAL_1_SEL_OUTPUT_PIO_CTRL $HOST_SYS_BITSERIAL_1_SEL_OUTPUT_PIO_CTRL; // RW   7 bits
.CONST $HOST_SYS_BITSERIAL_1_DATA_INPUT_PIO_CTRL 0x6004D034; // RW   7 bits
.CONST $_HOST_SYS_BITSERIAL_1_DATA_INPUT_PIO_CTRL $HOST_SYS_BITSERIAL_1_DATA_INPUT_PIO_CTRL; // RW   7 bits
.CONST $HOST_SYS_BITSERIAL_1_CLK_INPUT_PIO_CTRL 0x6004D038; // RW   7 bits
.CONST $_HOST_SYS_BITSERIAL_1_CLK_INPUT_PIO_CTRL $HOST_SYS_BITSERIAL_1_CLK_INPUT_PIO_CTRL; // RW   7 bits
.CONST $HOST_SYS_BITSERIAL_1_SEL_INPUT_PIO_CTRL 0x6004D03C; // RW   7 bits
.CONST $_HOST_SYS_BITSERIAL_1_SEL_INPUT_PIO_CTRL $HOST_SYS_BITSERIAL_1_SEL_INPUT_PIO_CTRL; // RW   7 bits
.CONST $HOST_SYS_SDIO_SIDEBAND_INTERRUPT_OUTPUT_PIO_CTRL 0x6004D040; // RW   7 bits
.CONST $_HOST_SYS_SDIO_SIDEBAND_INTERRUPT_OUTPUT_PIO_CTRL $HOST_SYS_SDIO_SIDEBAND_INTERRUPT_OUTPUT_PIO_CTRL; // RW   7 bits
.CONST $HOST_SYS_DEBUG_SELECT                0x6004D044; // RW   8 bits
.CONST $_HOST_SYS_DEBUG_SELECT               $HOST_SYS_DEBUG_SELECT; // RW   8 bits
.CONST $HOST_SYS_BTM_DEBUG_SELECT            0x6004D048; // RW   6 bits
.CONST $_HOST_SYS_BTM_DEBUG_SELECT           $HOST_SYS_BTM_DEBUG_SELECT; // RW   6 bits
.CONST $HOST_SYS_CLK_80M_DIV                 0x6004D04C; // RW   8 bits
.CONST $_HOST_SYS_CLK_80M_DIV                $HOST_SYS_CLK_80M_DIV; // RW   8 bits
.CONST $HOST_SYS_POWER_ENABLES               0x6004D050; // RW   5 bits
.CONST $_HOST_SYS_POWER_ENABLES              $HOST_SYS_POWER_ENABLES; // RW   5 bits
.CONST $HOST_SYS_POWER_STATUS                0x6004D054; //  R   5 bits
.CONST $_HOST_SYS_POWER_STATUS               $HOST_SYS_POWER_STATUS; //  R   5 bits
.CONST $HOST_SYS_HIFS_BUILT                  0x6004D058; //  R   5 bits
.CONST $_HOST_SYS_HIFS_BUILT                 $HOST_SYS_HIFS_BUILT; //  R   5 bits
.CONST $HOST_SYS_REG_ACCESS_SUBSYS_IN_ADDR_EN 0x6004D05C; // RW  16 bits
.CONST $_HOST_SYS_REG_ACCESS_SUBSYS_IN_ADDR_EN $HOST_SYS_REG_ACCESS_SUBSYS_IN_ADDR_EN; // RW  16 bits
.CONST $HOST_SYS_UART_DATA_OUTPUT_PIO_CTRL   0x6004D060; // RW   7 bits
.CONST $_HOST_SYS_UART_DATA_OUTPUT_PIO_CTRL  $HOST_SYS_UART_DATA_OUTPUT_PIO_CTRL; // RW   7 bits
.CONST $HOST_SYS_UART_RTSB_OUTPUT_PIO_CTRL   0x6004D064; // RW   7 bits
.CONST $_HOST_SYS_UART_RTSB_OUTPUT_PIO_CTRL  $HOST_SYS_UART_RTSB_OUTPUT_PIO_CTRL; // RW   7 bits
.CONST $HOST_SYS_UART_DATA_INPUT_PIO_CTRL    0x6004D068; // RW   7 bits
.CONST $_HOST_SYS_UART_DATA_INPUT_PIO_CTRL   $HOST_SYS_UART_DATA_INPUT_PIO_CTRL; // RW   7 bits
.CONST $HOST_SYS_UART_CTSB_INPUT_PIO_CTRL    0x6004D06C; // RW   7 bits
.CONST $_HOST_SYS_UART_CTSB_INPUT_PIO_CTRL   $HOST_SYS_UART_CTSB_INPUT_PIO_CTRL; // RW   7 bits
.CONST $HOST_SYS_MMU_RAM_SEQ_TIMING_REG0     0x6004D074; // RW  16 bits
.CONST $_HOST_SYS_MMU_RAM_SEQ_TIMING_REG0    $HOST_SYS_MMU_RAM_SEQ_TIMING_REG0; // RW  16 bits
.CONST $HOST_SYS_MMU_RAM_SEQ_TIMING_REG1     0x6004D078; // RW  16 bits
.CONST $_HOST_SYS_MMU_RAM_SEQ_TIMING_REG1    $HOST_SYS_MMU_RAM_SEQ_TIMING_REG1; // RW  16 bits
.CONST $HOST_SYS_MMU_RAM_SEQ_TIMING_REG2     0x6004D07C; // RW  12 bits
.CONST $_HOST_SYS_MMU_RAM_SEQ_TIMING_REG2    $HOST_SYS_MMU_RAM_SEQ_TIMING_REG2; // RW  12 bits
.CONST $USB_TX_PREFETCH_RAM_16EPS_RAM0_EMA   0x6004D08C; // RW   5 bits
.CONST $_USB_TX_PREFETCH_RAM_16EPS_RAM0_EMA  $USB_TX_PREFETCH_RAM_16EPS_RAM0_EMA; // RW   5 bits
.CONST $USB_TX_PREFETCH_RAM_16EPS_RAM1_EMA   0x6004D090; // RW   5 bits
.CONST $_USB_TX_PREFETCH_RAM_16EPS_RAM1_EMA  $USB_TX_PREFETCH_RAM_16EPS_RAM1_EMA; // RW   5 bits
.CONST $USB_TX_PREFETCH_RAM_16EPS_RAM2_EMA   0x6004D094; // RW   5 bits
.CONST $_USB_TX_PREFETCH_RAM_16EPS_RAM2_EMA  $USB_TX_PREFETCH_RAM_16EPS_RAM2_EMA; // RW   5 bits
.CONST $USB_TX_PREFETCH_RAM_16EPS_RAM3_EMA   0x6004D098; // RW   5 bits
.CONST $_USB_TX_PREFETCH_RAM_16EPS_RAM3_EMA  $USB_TX_PREFETCH_RAM_16EPS_RAM3_EMA; // RW   5 bits
.CONST $MM_DOLOOP_START                      0xFFFF8000; // RW  32 bits
.CONST $_MM_DOLOOP_START                     $MM_DOLOOP_START; // RW  32 bits
.CONST $MM_DOLOOP_END                        0xFFFF8004; // RW  32 bits
.CONST $_MM_DOLOOP_END                       $MM_DOLOOP_END; // RW  32 bits
.CONST $MM_QUOTIENT                          0xFFFF8008; // RW  32 bits
.CONST $_MM_QUOTIENT                         $MM_QUOTIENT; // RW  32 bits
.CONST $MM_REM                               0xFFFF800C; // RW  32 bits
.CONST $_MM_REM                              $MM_REM; // RW  32 bits
.CONST $MM_RINTLINK                          0xFFFF8010; // RW  32 bits
.CONST $_MM_RINTLINK                         $MM_RINTLINK; // RW  32 bits
.CONST $ARITHMETIC_MODE                      0xFFFF8014; // RW   5 bits
.CONST $_ARITHMETIC_MODE                     $ARITHMETIC_MODE; // RW   5 bits
.CONST $STACK_START_ADDR                     0xFFFF8018; // RW  32 bits
.CONST $_STACK_START_ADDR                    $STACK_START_ADDR; // RW  32 bits
.CONST $STACK_END_ADDR                       0xFFFF801C; // RW  32 bits
.CONST $_STACK_END_ADDR                      $STACK_END_ADDR; // RW  32 bits
.CONST $STACK_POINTER                        0xFFFF8020; // RW  32 bits
.CONST $_STACK_POINTER                       $STACK_POINTER; // RW  32 bits
.CONST $STACK_OVERFLOW_PC                    0xFFFF8024; //  R  32 bits
.CONST $_STACK_OVERFLOW_PC                   $STACK_OVERFLOW_PC; //  R  32 bits
.CONST $FRAME_POINTER                        0xFFFF8028; // RW  32 bits
.CONST $_FRAME_POINTER                       $FRAME_POINTER; // RW  32 bits
.CONST $BITREVERSE_VAL                       0xFFFF802C; // RW  32 bits
.CONST $_BITREVERSE_VAL                      $BITREVERSE_VAL; // RW  32 bits
.CONST $BITREVERSE_DATA                      0xFFFF8030; //  R  32 bits
.CONST $_BITREVERSE_DATA                     $BITREVERSE_DATA; //  R  32 bits
.CONST $BITREVERSE_DATA16                    0xFFFF8034; //  R  32 bits
.CONST $_BITREVERSE_DATA16                   $BITREVERSE_DATA16; //  R  32 bits
.CONST $BITREVERSE_ADDR                      0xFFFF8038; //  R  32 bits
.CONST $_BITREVERSE_ADDR                     $BITREVERSE_ADDR; //  R  32 bits
.CONST $NUM_RUN_CLKS                         0xFFFF803C; //  R  32 bits
.CONST $_NUM_RUN_CLKS                        $NUM_RUN_CLKS; //  R  32 bits
.CONST $NUM_INSTRS                           0xFFFF8040; //  R  32 bits
.CONST $_NUM_INSTRS                          $NUM_INSTRS; //  R  32 bits
.CONST $NUM_CORE_STALLS                      0xFFFF8044; //  R  32 bits
.CONST $_NUM_CORE_STALLS                     $NUM_CORE_STALLS; //  R  32 bits
.CONST $NUM_MEM_ACCESS_STALLS                0xFFFF8048; //  R  32 bits
.CONST $_NUM_MEM_ACCESS_STALLS               $NUM_MEM_ACCESS_STALLS; //  R  32 bits
.CONST $NUM_INSTR_EXPAND_STALLS              0xFFFF804C; //  R  32 bits
.CONST $_NUM_INSTR_EXPAND_STALLS             $NUM_INSTR_EXPAND_STALLS; //  R  32 bits
.CONST $DBG_COUNTERS_EN                      0xFFFF8050; // RW   1 bits
.CONST $_DBG_COUNTERS_EN                     $DBG_COUNTERS_EN; // RW   1 bits
.CONST $PC_STATUS                            0xFFFF8054; //  R  32 bits
.CONST $_PC_STATUS                           $PC_STATUS; //  R  32 bits
.CONST $TEST_REG_0                           0xFFFF8058; // RW  32 bits
.CONST $_TEST_REG_0                          $TEST_REG_0; // RW  32 bits
.CONST $TEST_REG_1                           0xFFFF805C; // RW  32 bits
.CONST $_TEST_REG_1                          $TEST_REG_1; // RW  32 bits
.CONST $TEST_REG_2                           0xFFFF8060; // RW  32 bits
.CONST $_TEST_REG_2                          $TEST_REG_2; // RW  32 bits
.CONST $TEST_REG_3                           0xFFFF8064; // RW  32 bits
.CONST $_TEST_REG_3                          $TEST_REG_3; // RW  32 bits
.CONST $CLOCK_DIVIDE_RATE                    0xFFFF8080; // RW   2 bits
.CONST $_CLOCK_DIVIDE_RATE                   $CLOCK_DIVIDE_RATE; // RW   2 bits
.CONST $PMWIN_ENABLE                         0xFFFF8084; // RW   1 bits
.CONST $_PMWIN_ENABLE                        $PMWIN_ENABLE; // RW   1 bits
.CONST $PROC_DEEP_SLEEP_EN                   0xFFFF8088; // RW   1 bits
.CONST $_PROC_DEEP_SLEEP_EN                  $PROC_DEEP_SLEEP_EN; // RW   1 bits
.CONST $PROCESSOR_ID                         0xFFFF808C; //  R   1 bits
.CONST $_PROCESSOR_ID                        $PROCESSOR_ID; //  R   1 bits
.CONST $CLOCK_STOP_WIND_DOWN_SEQUENCE_EN     0xFFFF8094; // RW   1 bits
.CONST $_CLOCK_STOP_WIND_DOWN_SEQUENCE_EN    $CLOCK_STOP_WIND_DOWN_SEQUENCE_EN; // RW   1 bits
.CONST $ALLOW_GOTO_SHALLOW_SLEEP             0xFFFF8098; // RW   1 bits
.CONST $_ALLOW_GOTO_SHALLOW_SLEEP            $ALLOW_GOTO_SHALLOW_SLEEP; // RW   1 bits
.CONST $GOTO_SHALLOW_SLEEP                   0xFFFF809C; //  W   1 bits
.CONST $_GOTO_SHALLOW_SLEEP                  $GOTO_SHALLOW_SLEEP; //  W   1 bits
.CONST $SHALLOW_SLEEP_STATUS                 0xFFFF80A0; //  R   1 bits
.CONST $_SHALLOW_SLEEP_STATUS                $SHALLOW_SLEEP_STATUS; //  R   1 bits
.CONST $DISABLE_MUTEX_AND_ACCESS_IMMUNITY    0xFFFF80A4; // RW   1 bits
.CONST $_DISABLE_MUTEX_AND_ACCESS_IMMUNITY   $DISABLE_MUTEX_AND_ACCESS_IMMUNITY; // RW   1 bits
.CONST $CLOCK_CONT_SHALLOW_SLEEP_RATE        0xFFFF80A8; // RW   8 bits
.CONST $_CLOCK_CONT_SHALLOW_SLEEP_RATE       $CLOCK_CONT_SHALLOW_SLEEP_RATE; // RW   8 bits
.CONST $INT_GBL_ENABLE                       0xFFFF8100; // RW   1 bits
.CONST $_INT_GBL_ENABLE                      $INT_GBL_ENABLE; // RW   1 bits
.CONST $INT_UNBLOCK                          0xFFFF8104; // RW   1 bits
.CONST $_INT_UNBLOCK                         $INT_UNBLOCK; // RW   1 bits
.CONST $INT_ADDR                             0xFFFF8108; // RW  32 bits
.CONST $_INT_ADDR                            $INT_ADDR; // RW  32 bits
.CONST $INT_CLK_SWITCH_EN                    0xFFFF810C; // RW   1 bits
.CONST $_INT_CLK_SWITCH_EN                   $INT_CLK_SWITCH_EN; // RW   1 bits
.CONST $INT_CLOCK_DIVIDE_RATE                0xFFFF8110; // RW   2 bits
.CONST $_INT_CLOCK_DIVIDE_RATE               $INT_CLOCK_DIVIDE_RATE; // RW   2 bits
.CONST $INT_ACK                              0xFFFF8114; // RW   1 bits
.CONST $_INT_ACK                             $INT_ACK; // RW   1 bits
.CONST $INT_SW0_EVENT                        0xFFFF8118; // RW   1 bits
.CONST $_INT_SW0_EVENT                       $INT_SW0_EVENT; // RW   1 bits
.CONST $INT_SW1_EVENT                        0xFFFF811C; // RW   1 bits
.CONST $_INT_SW1_EVENT                       $INT_SW1_EVENT; // RW   1 bits
.CONST $INT_SELECT                           0xFFFF8120; // RW   5 bits
.CONST $_INT_SELECT                          $INT_SELECT; // RW   5 bits
.CONST $INT_PRIORITY                         0xFFFF8124; // RW   2 bits
.CONST $_INT_PRIORITY                        $INT_PRIORITY; // RW   2 bits
.CONST $INT_LOAD_INFO                        0xFFFF8128; // RW  20 bits
.CONST $_INT_LOAD_INFO                       $INT_LOAD_INFO; // RW  20 bits
.CONST $INT_SAVE_INFO                        0xFFFF812C; //  R  22 bits
.CONST $_INT_SAVE_INFO                       $INT_SAVE_INFO; //  R  22 bits
.CONST $INT_SOURCE                           0xFFFF8130; //  R   5 bits
.CONST $_INT_SOURCE                          $INT_SOURCE; //  R   5 bits
.CONST $INT_STATUS                           0xFFFF8134; //  R  32 bits
.CONST $_INT_STATUS                          $INT_STATUS; //  R  32 bits
.CONST $INT_SOURCES_EN                       0xFFFF8138; // RW  32 bits
.CONST $_INT_SOURCES_EN                      $INT_SOURCES_EN; // RW  32 bits
.CONST $INT_BLOCK_PRIORITY                   0xFFFF813C; // RW   2 bits
.CONST $_INT_BLOCK_PRIORITY                  $INT_BLOCK_PRIORITY; // RW   2 bits
.CONST $TIMER_TIME                           0xFFFF8180; //  R  32 bits
.CONST $_TIMER_TIME                          $TIMER_TIME; //  R  32 bits
.CONST $TIMER1_EN                            0xFFFF8184; // RW   1 bits
.CONST $_TIMER1_EN                           $TIMER1_EN; // RW   1 bits
.CONST $TIMER2_EN                            0xFFFF8188; // RW   1 bits
.CONST $_TIMER2_EN                           $TIMER2_EN; // RW   1 bits
.CONST $TIMER1_TRIGGER                       0xFFFF818C; // RW  32 bits
.CONST $_TIMER1_TRIGGER                      $TIMER1_TRIGGER; // RW  32 bits
.CONST $TIMER2_TRIGGER                       0xFFFF8190; // RW  32 bits
.CONST $_TIMER2_TRIGGER                      $TIMER2_TRIGGER; // RW  32 bits
.CONST $DOLOOP_CACHE_CONFIG                  0xFFFF8200; // RW   2 bits
.CONST $_DOLOOP_CACHE_CONFIG                 $DOLOOP_CACHE_CONFIG; // RW   2 bits
.CONST $DOLOOP_CACHE_HIT_COUNT               0xFFFF8204; //  R  32 bits
.CONST $_DOLOOP_CACHE_HIT_COUNT              $DOLOOP_CACHE_HIT_COUNT; //  R  32 bits
.CONST $DOLOOP_CACHE_FILL_COUNT              0xFFFF8208; //  R  32 bits
.CONST $_DOLOOP_CACHE_FILL_COUNT             $DOLOOP_CACHE_FILL_COUNT; //  R  32 bits
.CONST $EXCEPTION_EN                         0xFFFF8280; // RW   2 bits
.CONST $_EXCEPTION_EN                        $EXCEPTION_EN; // RW   2 bits
.CONST $EXCEPTION_TYPE                       0xFFFF8284; //  R   4 bits
.CONST $_EXCEPTION_TYPE                      $EXCEPTION_TYPE; //  R   4 bits
.CONST $PROG_EXCEPTION_REGION_ENABLE         0xFFFF82A0; // RW   4 bits
.CONST $_PROG_EXCEPTION_REGION_ENABLE        $PROG_EXCEPTION_REGION_ENABLE; // RW   4 bits
.CONST $PM_PROG_EXCEPTION_REGION_START_ADDR  0xFFFF82A4; // RW  32 bits
.CONST $_PM_PROG_EXCEPTION_REGION_START_ADDR $PM_PROG_EXCEPTION_REGION_START_ADDR; // RW  32 bits
.CONST $PM_PROG_EXCEPTION_REGION_END_ADDR    0xFFFF82A8; // RW  32 bits
.CONST $_PM_PROG_EXCEPTION_REGION_END_ADDR   $PM_PROG_EXCEPTION_REGION_END_ADDR; // RW  32 bits
.CONST $DM1_PROG_EXCEPTION_REGION_START_ADDR 0xFFFF82AC; // RW  32 bits
.CONST $_DM1_PROG_EXCEPTION_REGION_START_ADDR $DM1_PROG_EXCEPTION_REGION_START_ADDR; // RW  32 bits
.CONST $DM1_PROG_EXCEPTION_REGION_END_ADDR   0xFFFF82B0; // RW  32 bits
.CONST $_DM1_PROG_EXCEPTION_REGION_END_ADDR  $DM1_PROG_EXCEPTION_REGION_END_ADDR; // RW  32 bits
.CONST $DM2_PROG_EXCEPTION_REGION_START_ADDR 0xFFFF82B4; // RW  32 bits
.CONST $_DM2_PROG_EXCEPTION_REGION_START_ADDR $DM2_PROG_EXCEPTION_REGION_START_ADDR; // RW  32 bits
.CONST $DM2_PROG_EXCEPTION_REGION_END_ADDR   0xFFFF82B8; // RW  32 bits
.CONST $_DM2_PROG_EXCEPTION_REGION_END_ADDR  $DM2_PROG_EXCEPTION_REGION_END_ADDR; // RW  32 bits
.CONST $EXCEPTION_PC                         0xFFFF82BC; //  R  32 bits
.CONST $_EXCEPTION_PC                        $EXCEPTION_PC; //  R  32 bits
.CONST $PREFETCH_CONFIG                      0xFFFF8320; // RW   1 bits
.CONST $_PREFETCH_CONFIG                     $PREFETCH_CONFIG; // RW   1 bits
.CONST $PREFETCH_FLUSH                       0xFFFF8324; // RW   1 bits
.CONST $_PREFETCH_FLUSH                      $PREFETCH_FLUSH; // RW   1 bits
.CONST $PREFETCH_REQUEST_COUNT               0xFFFF8328; //  R  32 bits
.CONST $_PREFETCH_REQUEST_COUNT              $PREFETCH_REQUEST_COUNT; //  R  32 bits
.CONST $PREFETCH_PREFETCH_COUNT              0xFFFF832C; //  R  32 bits
.CONST $_PREFETCH_PREFETCH_COUNT             $PREFETCH_PREFETCH_COUNT; //  R  32 bits
.CONST $PREFETCH_WAIT_OUT_COUNT              0xFFFF8330; //  R  32 bits
.CONST $_PREFETCH_WAIT_OUT_COUNT             $PREFETCH_WAIT_OUT_COUNT; //  R  32 bits
.CONST $PREFETCH_DEBUG                       0xFFFF8334; //  R  25 bits
.CONST $_PREFETCH_DEBUG                      $PREFETCH_DEBUG; //  R  25 bits
.CONST $PREFETCH_DEBUG_ADDR                  0xFFFF8338; //  R  32 bits
.CONST $_PREFETCH_DEBUG_ADDR                 $PREFETCH_DEBUG_ADDR; //  R  32 bits
.CONST $APPS_SYS_TEST_REG                    0xFFFF9000; // RW  32 bits
.CONST $_APPS_SYS_TEST_REG                   $APPS_SYS_TEST_REG; // RW  32 bits
.CONST $APPS_SYS_MUTEX_LOCK                  0xFFFF9004; // RW   4 bits
.CONST $_APPS_SYS_MUTEX_LOCK                 $APPS_SYS_MUTEX_LOCK; // RW   4 bits
.CONST $APPS_SYS_ACCESS_CTRL                 0xFFFF9008; // RW   4 bits
.CONST $_APPS_SYS_ACCESS_CTRL                $APPS_SYS_ACCESS_CTRL; // RW   4 bits
.CONST $CLKGEN_TIMER_ENABLES                 0xFFFF9010; // RW   2 bits
.CONST $_CLKGEN_TIMER_ENABLES                $CLKGEN_TIMER_ENABLES; // RW   2 bits
.CONST $CLKGEN_CORE_CLK_RATE                 0xFFFF9014; // RW   4 bits
.CONST $_CLKGEN_CORE_CLK_RATE                $CLKGEN_CORE_CLK_RATE; // RW   4 bits
.CONST $CLKGEN_DEBUG                         0xFFFF9018; // RW   4 bits
.CONST $_CLKGEN_DEBUG                        $CLKGEN_DEBUG; // RW   4 bits
.CONST $CLKGEN_TIMER_FAST_STATUS             0xFFFF9020; //  R  16 bits
.CONST $_CLKGEN_TIMER_FAST_STATUS            $CLKGEN_TIMER_FAST_STATUS; //  R  16 bits
.CONST $CLKGEN_ENABLES                       0xFFFF9028; // RW  30 bits
.CONST $_CLKGEN_ENABLES                      $CLKGEN_ENABLES; // RW  30 bits
.CONST $CLKGEN_STATUS_SLOW_CLK               0xFFFF9040; //  R   1 bits
.CONST $_CLKGEN_STATUS_SLOW_CLK              $CLKGEN_STATUS_SLOW_CLK; //  R   1 bits
.CONST $CLKGEN_SDIO_HOST_CLK_CONFIG          0xFFFF9044; // RW   4 bits
.CONST $_CLKGEN_SDIO_HOST_CLK_CONFIG         $CLKGEN_SDIO_HOST_CLK_CONFIG; // RW   4 bits
.CONST $BUS_INT_SELECT                       0xFFFF9050; // RW   4 bits
.CONST $_BUS_INT_SELECT                      $BUS_INT_SELECT; // RW   4 bits
.CONST $BUS_INT_MASK                         0xFFFF9054; // RW  16 bits
.CONST $_BUS_INT_MASK                        $BUS_INT_MASK; // RW  16 bits
.CONST $BUS_INT_CLEAR                        0xFFFF9058; // RW  16 bits
.CONST $_BUS_INT_CLEAR                       $BUS_INT_CLEAR; // RW  16 bits
.CONST $BUS_INT_STATUS                       0xFFFF905C; //  R  16 bits
.CONST $_BUS_INT_STATUS                      $BUS_INT_STATUS; //  R  16 bits
.CONST $BUS_INT_CONFIG                       0xFFFF9060; // RW  10 bits
.CONST $_BUS_INT_CONFIG                      $BUS_INT_CONFIG; // RW  10 bits
.CONST $BUS_INT_CONFIG_STATUS                0xFFFF9064; //  R  10 bits
.CONST $_BUS_INT_CONFIG_STATUS               $BUS_INT_CONFIG_STATUS; //  R  10 bits
.CONST $BUS_INT_MASK_STATUS                  0xFFFF9068; //  R  16 bits
.CONST $_BUS_INT_MASK_STATUS                 $BUS_INT_MASK_STATUS; //  R  16 bits
.CONST $BUS_INT_SEND_INT_CONFIG              0xFFFF906C; // RW  12 bits
.CONST $_BUS_INT_SEND_INT_CONFIG             $BUS_INT_SEND_INT_CONFIG; // RW  12 bits
.CONST $BUS_INT_SEND_INT_STATUS_FIELD        0xFFFF9070; // RW  16 bits
.CONST $_BUS_INT_SEND_INT_STATUS_FIELD       $BUS_INT_SEND_INT_STATUS_FIELD; // RW  16 bits
.CONST $BUS_INT_SEND_INT_SEND_STATUS         0xFFFF9074; //  R   2 bits
.CONST $_BUS_INT_SEND_INT_SEND_STATUS        $BUS_INT_SEND_INT_SEND_STATUS; //  R   2 bits
.CONST $BUS_INT_MUTEX_LOCK                   0xFFFF9078; // RW   4 bits
.CONST $_BUS_INT_MUTEX_LOCK                  $BUS_INT_MUTEX_LOCK; // RW   4 bits
.CONST $BUS_INT_ACCESS_CTRL                  0xFFFF907C; // RW   4 bits
.CONST $_BUS_INT_ACCESS_CTRL                 $BUS_INT_ACCESS_CTRL; // RW   4 bits
.CONST $SUB_SYS_CHIP_VERSION                 0xFFFF9100; //  R  16 bits
.CONST $_SUB_SYS_CHIP_VERSION                $SUB_SYS_CHIP_VERSION; //  R  16 bits
.CONST $SUB_SYS_REG_SRC_HASH                 0xFFFF9104; //  R  16 bits
.CONST $_SUB_SYS_REG_SRC_HASH                $SUB_SYS_REG_SRC_HASH; //  R  16 bits
.CONST $SUB_SYS_DEBUG_SELECT_LOW             0xFFFF9118; // RW   7 bits
.CONST $_SUB_SYS_DEBUG_SELECT_LOW            $SUB_SYS_DEBUG_SELECT_LOW; // RW   7 bits
.CONST $SUB_SYS_DEBUG_SELECT_HIGH            0xFFFF911C; // RW   7 bits
.CONST $_SUB_SYS_DEBUG_SELECT_HIGH           $SUB_SYS_DEBUG_SELECT_HIGH; // RW   7 bits
.CONST $SUB_SYS_DEBUG_SELECT_SHIFT           0xFFFF9120; // RW   2 bits
.CONST $_SUB_SYS_DEBUG_SELECT_SHIFT          $SUB_SYS_DEBUG_SELECT_SHIFT; // RW   2 bits
.CONST $SUB_SYS_DEBUG_STATUS                 0xFFFF9124; //  R  32 bits
.CONST $_SUB_SYS_DEBUG_STATUS                $SUB_SYS_DEBUG_STATUS; //  R  32 bits
.CONST $SUB_SYS_TRANSACTION_MUX_DBG_SEL      0xFFFF9128; // RW   6 bits
.CONST $_SUB_SYS_TRANSACTION_MUX_DBG_SEL     $SUB_SYS_TRANSACTION_MUX_DBG_SEL; // RW   6 bits
.CONST $SUB_SYS_RST_STATUS                   0xFFFF9130; // RW   3 bits
.CONST $_SUB_SYS_RST_STATUS                  $SUB_SYS_RST_STATUS; // RW   3 bits
.CONST $SUB_SYS_ID                           0xFFFF9150; //  R   4 bits
.CONST $_SUB_SYS_ID                          $SUB_SYS_ID; //  R   4 bits
.CONST $VM_INTERCONNECT_MUX_DEBUG_ENABLE     0xFFFF9160; // RW   1 bits
.CONST $_VM_INTERCONNECT_MUX_DEBUG_ENABLE    $VM_INTERCONNECT_MUX_DEBUG_ENABLE; // RW   1 bits
.CONST $RAM_SEQUENCER_ACTIVE_STATUS          0xFFFF9164; //  R  11 bits
.CONST $_RAM_SEQUENCER_ACTIVE_STATUS         $RAM_SEQUENCER_ACTIVE_STATUS; //  R  11 bits
.CONST $APPS_SYS_TBUS_WINDOW_IDS             0xFFFF9188; // RW   8 bits
.CONST $_APPS_SYS_TBUS_WINDOW_IDS            $APPS_SYS_TBUS_WINDOW_IDS; // RW   8 bits
.CONST $APPS_SYS_TBUS_WINDOW_EN              0xFFFF918C; // RW   2 bits
.CONST $_APPS_SYS_TBUS_WINDOW_EN             $APPS_SYS_TBUS_WINDOW_EN; // RW   2 bits
.CONST $APPS_SYS_CPU0_TCM_REMAP_CONTROLS     0xFFFF9190; // RW   4 bits
.CONST $_APPS_SYS_CPU0_TCM_REMAP_CONTROLS    $APPS_SYS_CPU0_TCM_REMAP_CONTROLS; // RW   4 bits
.CONST $APPS_SYS_CPU1_TCM_REMAP_CONTROLS     0xFFFF9194; // RW   4 bits
.CONST $_APPS_SYS_CPU1_TCM_REMAP_CONTROLS    $APPS_SYS_CPU1_TCM_REMAP_CONTROLS; // RW   4 bits
.CONST $APPS_SYS_TCM_LOCK                    0xFFFF9198; // RW   2 bits
.CONST $_APPS_SYS_TCM_LOCK                   $APPS_SYS_TCM_LOCK; // RW   2 bits
.CONST $APPS_FORCE_PWM_MODE_REQ              0xFFFF9278; // RW   2 bits
.CONST $_APPS_FORCE_PWM_MODE_REQ             $APPS_FORCE_PWM_MODE_REQ; // RW   2 bits
.CONST $APPS_SMPS_IN_PWM_MODE_STATUS         0xFFFF927C; //  R   2 bits
.CONST $_APPS_SMPS_IN_PWM_MODE_STATUS        $APPS_SMPS_IN_PWM_MODE_STATUS; //  R   2 bits
.CONST $APPS_SYS_PIO_DRIVE                   0xFFFF93CC; // RW  72 bits
.CONST $_APPS_SYS_PIO_DRIVE                  $APPS_SYS_PIO_DRIVE; // RW  72 bits
.CONST $APPS_SYS_PIO_DRIVE_WORD0             0xFFFF93CC; // RW 
.CONST $_APPS_SYS_PIO_DRIVE_WORD0            $APPS_SYS_PIO_DRIVE_WORD0; // RW 
.CONST $APPS_SYS_PIO_DRIVE_WORD1             0xFFFF93D0; // RW 
.CONST $_APPS_SYS_PIO_DRIVE_WORD1            $APPS_SYS_PIO_DRIVE_WORD1; // RW 
.CONST $APPS_SYS_PIO_DRIVE_WORD2             0xFFFF93D4; // RW 
.CONST $_APPS_SYS_PIO_DRIVE_WORD2            $APPS_SYS_PIO_DRIVE_WORD2; // RW 
.CONST $APPS_SYS_PIO_DRIVE_ENABLE            0xFFFF93D8; // RW  72 bits
.CONST $_APPS_SYS_PIO_DRIVE_ENABLE           $APPS_SYS_PIO_DRIVE_ENABLE; // RW  72 bits
.CONST $APPS_SYS_PIO_DRIVE_ENABLE_WORD0      0xFFFF93D8; // RW 
.CONST $_APPS_SYS_PIO_DRIVE_ENABLE_WORD0     $APPS_SYS_PIO_DRIVE_ENABLE_WORD0; // RW 
.CONST $APPS_SYS_PIO_DRIVE_ENABLE_WORD1      0xFFFF93DC; // RW 
.CONST $_APPS_SYS_PIO_DRIVE_ENABLE_WORD1     $APPS_SYS_PIO_DRIVE_ENABLE_WORD1; // RW 
.CONST $APPS_SYS_PIO_DRIVE_ENABLE_WORD2      0xFFFF93E0; // RW 
.CONST $_APPS_SYS_PIO_DRIVE_ENABLE_WORD2     $APPS_SYS_PIO_DRIVE_ENABLE_WORD2; // RW 
.CONST $APPS_SYS_PIO_STATUS                  0xFFFF93E4; //  R  72 bits
.CONST $_APPS_SYS_PIO_STATUS                 $APPS_SYS_PIO_STATUS; //  R  72 bits
.CONST $APPS_SYS_PIO_STATUS_WORD0            0xFFFF93E4; //  R 
.CONST $_APPS_SYS_PIO_STATUS_WORD0           $APPS_SYS_PIO_STATUS_WORD0; //  R 
.CONST $APPS_SYS_PIO_STATUS_WORD1            0xFFFF93E8; //  R 
.CONST $_APPS_SYS_PIO_STATUS_WORD1           $APPS_SYS_PIO_STATUS_WORD1; //  R 
.CONST $APPS_SYS_PIO_STATUS_WORD2            0xFFFF93EC; //  R 
.CONST $_APPS_SYS_PIO_STATUS_WORD2           $APPS_SYS_PIO_STATUS_WORD2; //  R 
.CONST $APPS_SYS_PIO_MUX                     0xFFFF93F0; // RW  72 bits
.CONST $_APPS_SYS_PIO_MUX                    $APPS_SYS_PIO_MUX; // RW  72 bits
.CONST $APPS_SYS_PIO_MUX_WORD0               0xFFFF93F0; // RW 
.CONST $_APPS_SYS_PIO_MUX_WORD0              $APPS_SYS_PIO_MUX_WORD0; // RW 
.CONST $APPS_SYS_PIO_MUX_WORD1               0xFFFF93F4; // RW 
.CONST $_APPS_SYS_PIO_MUX_WORD1              $APPS_SYS_PIO_MUX_WORD1; // RW 
.CONST $APPS_SYS_PIO_MUX_WORD2               0xFFFF93F8; // RW 
.CONST $_APPS_SYS_PIO_MUX_WORD2              $APPS_SYS_PIO_MUX_WORD2; // RW 
.CONST $LED_EN                               0xFFFF9400; // RW   6 bits
.CONST $_LED_EN                              $LED_EN; // RW   6 bits
.CONST $LED_UPDATE                           0xFFFF9404; // RW   6 bits
.CONST $_LED_UPDATE                          $LED_UPDATE; // RW   6 bits
.CONST $LED_CONFIGURE                        0xFFFF9408; // RW   1 bits
.CONST $_LED_CONFIGURE                       $LED_CONFIGURE; // RW   1 bits
.CONST $LED_INDEX                            0xFFFF940C; // RW   4 bits
.CONST $_LED_INDEX                           $LED_INDEX; // RW   4 bits
.CONST $LED_PIN_CONFIG                       0xFFFF9410; // RW   2 bits
.CONST $_LED_PIN_CONFIG                      $LED_PIN_CONFIG; // RW   2 bits
.CONST $LED_MIN_LOW_CONFIG                   0xFFFF9414; // RW  16 bits
.CONST $_LED_MIN_LOW_CONFIG                  $LED_MIN_LOW_CONFIG; // RW  16 bits
.CONST $LED_MIN_HIGH_CONFIG                  0xFFFF9418; // RW  16 bits
.CONST $_LED_MIN_HIGH_CONFIG                 $LED_MIN_HIGH_CONFIG; // RW  16 bits
.CONST $LED_MAX_LOW_CONFIG                   0xFFFF941C; // RW  16 bits
.CONST $_LED_MAX_LOW_CONFIG                  $LED_MAX_LOW_CONFIG; // RW  16 bits
.CONST $LED_MAX_HIGH_CONFIG                  0xFFFF9420; // RW  16 bits
.CONST $_LED_MAX_HIGH_CONFIG                 $LED_MAX_HIGH_CONFIG; // RW  16 bits
.CONST $LED_HOLD_LOW_CONFIG                  0xFFFF9424; // RW  16 bits
.CONST $_LED_HOLD_LOW_CONFIG                 $LED_HOLD_LOW_CONFIG; // RW  16 bits
.CONST $LED_HOLD_HIGH_CONFIG                 0xFFFF9428; // RW  16 bits
.CONST $_LED_HOLD_HIGH_CONFIG                $LED_HOLD_HIGH_CONFIG; // RW  16 bits
.CONST $LED_RAMP_CONFIG                      0xFFFF942C; // RW  16 bits
.CONST $_LED_RAMP_CONFIG                     $LED_RAMP_CONFIG; // RW  16 bits
.CONST $LED_RAMP_SHIFT                       0xFFFF9430; // RW   3 bits
.CONST $_LED_RAMP_SHIFT                      $LED_RAMP_SHIFT; // RW   3 bits
.CONST $LED_START_UP_STATE                   0xFFFF9434; // RW   3 bits
.CONST $_LED_START_UP_STATE                  $LED_START_UP_STATE; // RW   3 bits
.CONST $LED_COUNTHOLD_VALUE                  0xFFFF9438; // RW  16 bits
.CONST $_LED_COUNTHOLD_VALUE                 $LED_COUNTHOLD_VALUE; // RW  16 bits
.CONST $LED_RAMP_CURRENT_LOW_CONFIG          0xFFFF943C; // RW  16 bits
.CONST $_LED_RAMP_CURRENT_LOW_CONFIG         $LED_RAMP_CURRENT_LOW_CONFIG; // RW  16 bits
.CONST $LED_RAMP_CURRENT_HIGH_CONFIG         0xFFFF9440; // RW  16 bits
.CONST $_LED_RAMP_CURRENT_HIGH_CONFIG        $LED_RAMP_CURRENT_HIGH_CONFIG; // RW  16 bits
.CONST $LED_SINGLE_SHOT_MODE                 0xFFFF9444; // RW   6 bits
.CONST $_LED_SINGLE_SHOT_MODE                $LED_SINGLE_SHOT_MODE; // RW   6 bits
.CONST $LED_SINGLE_SHOT_LOW_CONFIG           0xFFFF9448; // RW  16 bits
.CONST $_LED_SINGLE_SHOT_LOW_CONFIG          $LED_SINGLE_SHOT_LOW_CONFIG; // RW  16 bits
.CONST $LED_SINGLE_SHOT_HIGH_CONFIG          0xFFFF944C; // RW  16 bits
.CONST $_LED_SINGLE_SHOT_HIGH_CONFIG         $LED_SINGLE_SHOT_HIGH_CONFIG; // RW  16 bits
.CONST $LED_MIN_LOW_CONFIG_STATUS            0xFFFF9450; //  R  16 bits
.CONST $_LED_MIN_LOW_CONFIG_STATUS           $LED_MIN_LOW_CONFIG_STATUS; //  R  16 bits
.CONST $LED_MIN_HIGH_CONFIG_STATUS           0xFFFF9454; //  R  16 bits
.CONST $_LED_MIN_HIGH_CONFIG_STATUS          $LED_MIN_HIGH_CONFIG_STATUS; //  R  16 bits
.CONST $LED_MAX_LOW_CONFIG_STATUS            0xFFFF9458; //  R  16 bits
.CONST $_LED_MAX_LOW_CONFIG_STATUS           $LED_MAX_LOW_CONFIG_STATUS; //  R  16 bits
.CONST $LED_MAX_HIGH_CONFIG_STATUS           0xFFFF945C; //  R  16 bits
.CONST $_LED_MAX_HIGH_CONFIG_STATUS          $LED_MAX_HIGH_CONFIG_STATUS; //  R  16 bits
.CONST $LED_HOLD_LOW_CONFIG_STATUS           0xFFFF9460; //  R  16 bits
.CONST $_LED_HOLD_LOW_CONFIG_STATUS          $LED_HOLD_LOW_CONFIG_STATUS; //  R  16 bits
.CONST $LED_HOLD_HIGH_CONFIG_STATUS          0xFFFF9464; //  R  16 bits
.CONST $_LED_HOLD_HIGH_CONFIG_STATUS         $LED_HOLD_HIGH_CONFIG_STATUS; //  R  16 bits
.CONST $LED_RAMP_CONFIG_STATUS               0xFFFF9468; //  R  16 bits
.CONST $_LED_RAMP_CONFIG_STATUS              $LED_RAMP_CONFIG_STATUS; //  R  16 bits
.CONST $LED_PIN_CONFIG_STATUS                0xFFFF946C; //  R   2 bits
.CONST $_LED_PIN_CONFIG_STATUS               $LED_PIN_CONFIG_STATUS; //  R   2 bits
.CONST $LED_CTRL_SOFT_RESET                  0xFFFF9470; //  W   1 bits
.CONST $_LED_CTRL_SOFT_RESET                 $LED_CTRL_SOFT_RESET; //  W   1 bits
.CONST $LED_LOGARITHMIC_EN                   0xFFFF9474; // RW   1 bits
.CONST $_LED_LOGARITHMIC_EN                  $LED_LOGARITHMIC_EN; // RW   1 bits
.CONST $LED_LOGARITHMIC_OFFSET_HIGH          0xFFFF9478; // RW   4 bits
.CONST $_LED_LOGARITHMIC_OFFSET_HIGH         $LED_LOGARITHMIC_OFFSET_HIGH; // RW   4 bits
.CONST $LED_LOGARITHMIC_OFFSET_LOW           0xFFFF947C; // RW   4 bits
.CONST $_LED_LOGARITHMIC_OFFSET_LOW          $LED_LOGARITHMIC_OFFSET_LOW; // RW   4 bits
.CONST $LED_LOGARITHMIC_STATUS               0xFFFF9480; //  R  12 bits
.CONST $_LED_LOGARITHMIC_STATUS              $LED_LOGARITHMIC_STATUS; //  R  12 bits
.CONST $LED_CTRL_CLK_ENABLE                  0xFFFF9484; //  W   1 bits
.CONST $_LED_CTRL_CLK_ENABLE                 $LED_CTRL_CLK_ENABLE; //  W   1 bits
.CONST $LED_DEBUG_SELECT                     0xFFFF9488; // RW   4 bits
.CONST $_LED_DEBUG_SELECT                    $LED_DEBUG_SELECT; // RW   4 bits
.CONST $READ_DECRYPT_CONTROL                 0xFFFF9500; // RW  12 bits
.CONST $_READ_DECRYPT_CONTROL                $READ_DECRYPT_CONTROL; // RW  12 bits
.CONST $READ_DECRYPT_CLEARTEXT_BASE          0xFFFF9504; // RW  32 bits
.CONST $_READ_DECRYPT_CLEARTEXT_BASE         $READ_DECRYPT_CLEARTEXT_BASE; // RW  32 bits
.CONST $READ_DECRYPT_CLEARTEXT_SIZE          0xFFFF9508; // RW  32 bits
.CONST $_READ_DECRYPT_CLEARTEXT_SIZE         $READ_DECRYPT_CLEARTEXT_SIZE; // RW  32 bits
.CONST $READ_DECRYPT_IMAGE_ADDRESS_MASK      0xFFFF950C; // RW  16 bits
.CONST $_READ_DECRYPT_IMAGE_ADDRESS_MASK     $READ_DECRYPT_IMAGE_ADDRESS_MASK; // RW  16 bits
.CONST $READ_DECRYPT_KEY                     0xFFFF9510; // RW 128 bits
.CONST $_READ_DECRYPT_KEY                    $READ_DECRYPT_KEY; // RW 128 bits
.CONST $READ_DECRYPT_KEY_WORD0               0xFFFF9510; // RW 
.CONST $_READ_DECRYPT_KEY_WORD0              $READ_DECRYPT_KEY_WORD0; // RW 
.CONST $READ_DECRYPT_KEY_WORD1               0xFFFF9514; // RW 
.CONST $_READ_DECRYPT_KEY_WORD1              $READ_DECRYPT_KEY_WORD1; // RW 
.CONST $READ_DECRYPT_KEY_WORD2               0xFFFF9518; // RW 
.CONST $_READ_DECRYPT_KEY_WORD2              $READ_DECRYPT_KEY_WORD2; // RW 
.CONST $READ_DECRYPT_KEY_WORD3               0xFFFF951C; // RW 
.CONST $_READ_DECRYPT_KEY_WORD3              $READ_DECRYPT_KEY_WORD3; // RW 
.CONST $READ_DECRYPT_NONCE                   0xFFFF9520; // RW 128 bits
.CONST $_READ_DECRYPT_NONCE                  $READ_DECRYPT_NONCE; // RW 128 bits
.CONST $READ_DECRYPT_NONCE_WORD0             0xFFFF9520; // RW 
.CONST $_READ_DECRYPT_NONCE_WORD0            $READ_DECRYPT_NONCE_WORD0; // RW 
.CONST $READ_DECRYPT_NONCE_WORD1             0xFFFF9524; // RW 
.CONST $_READ_DECRYPT_NONCE_WORD1            $READ_DECRYPT_NONCE_WORD1; // RW 
.CONST $READ_DECRYPT_NONCE_WORD2             0xFFFF9528; // RW 
.CONST $_READ_DECRYPT_NONCE_WORD2            $READ_DECRYPT_NONCE_WORD2; // RW 
.CONST $READ_DECRYPT_NONCE_WORD3             0xFFFF952C; // RW 
.CONST $_READ_DECRYPT_NONCE_WORD3            $READ_DECRYPT_NONCE_WORD3; // RW 
.CONST $READ_DECRYPT_KEY_ENABLE              0xFFFF9530; // RW   1 bits
.CONST $_READ_DECRYPT_KEY_ENABLE             $READ_DECRYPT_KEY_ENABLE; // RW   1 bits
.CONST $READ_DECRYPT_MUTEX_LOCK              0xFFFF9534; // RW   4 bits
.CONST $_READ_DECRYPT_MUTEX_LOCK             $READ_DECRYPT_MUTEX_LOCK; // RW   4 bits
.CONST $READ_DECRYPT_ACCESS_CTRL             0xFFFF9538; // RW   4 bits
.CONST $_READ_DECRYPT_ACCESS_CTRL            $READ_DECRYPT_ACCESS_CTRL; // RW   4 bits
.CONST $READ_DECRYPT_PERFORMANCE             0xFFFF953C; //  R  32 bits
.CONST $_READ_DECRYPT_PERFORMANCE            $READ_DECRYPT_PERFORMANCE; //  R  32 bits
.CONST $SQIF_DATAPATH_STATUS                 0xFFFF9640; // RW   2 bits
.CONST $_SQIF_DATAPATH_STATUS                $SQIF_DATAPATH_STATUS; // RW   2 bits
.CONST $SQIF_DATAPATH_BANK                   0xFFFF9644; // RW  15 bits
.CONST $_SQIF_DATAPATH_BANK                  $SQIF_DATAPATH_BANK; // RW  15 bits
.CONST $SQIF_DATAPATH_PORT_CONTROL           0xFFFF9648; // RW   3 bits
.CONST $_SQIF_DATAPATH_PORT_CONTROL          $SQIF_DATAPATH_PORT_CONTROL; // RW   3 bits
.CONST $SQIF_DATAPATH_PORT_PARAMETERS        0xFFFF964C; // RW  14 bits
.CONST $_SQIF_DATAPATH_PORT_PARAMETERS       $SQIF_DATAPATH_PORT_PARAMETERS; // RW  14 bits
.CONST $SQIF_DATAPATH_MUTEX_LOCK             0xFFFF9650; // RW   4 bits
.CONST $_SQIF_DATAPATH_MUTEX_LOCK            $SQIF_DATAPATH_MUTEX_LOCK; // RW   4 bits
.CONST $SQIF_DATAPATH_ACCESS_CTRL            0xFFFF9654; // RW   4 bits
.CONST $_SQIF_DATAPATH_ACCESS_CTRL           $SQIF_DATAPATH_ACCESS_CTRL; // RW   4 bits
.CONST $SQIF_DATAPATH_BANKED_MUTEX_LOCK      0xFFFF9658; // RW   4 bits
.CONST $_SQIF_DATAPATH_BANKED_MUTEX_LOCK     $SQIF_DATAPATH_BANKED_MUTEX_LOCK; // RW   4 bits
.CONST $SQIF_DATAPATH_BANKED_ACCESS_CTRL     0xFFFF965C; // RW   4 bits
.CONST $_SQIF_DATAPATH_BANKED_ACCESS_CTRL    $SQIF_DATAPATH_BANKED_ACCESS_CTRL; // RW   4 bits
.CONST $SQIF_DATAPATH_TBUS_BRIDGE_ENABLE     0xFFFF9660; // RW   1 bits
.CONST $_SQIF_DATAPATH_TBUS_BRIDGE_ENABLE    $SQIF_DATAPATH_TBUS_BRIDGE_ENABLE; // RW   1 bits
.CONST $SQIF_DATAPATH_TBUS_BRIDGE_WINDOW_LOWER 0xFFFF9664; // RW  32 bits
.CONST $_SQIF_DATAPATH_TBUS_BRIDGE_WINDOW_LOWER $SQIF_DATAPATH_TBUS_BRIDGE_WINDOW_LOWER; // RW  32 bits
.CONST $SQIF_DATAPATH_TBUS_BRIDGE_WINDOW_UPPER 0xFFFF9668; // RW  32 bits
.CONST $_SQIF_DATAPATH_TBUS_BRIDGE_WINDOW_UPPER $SQIF_DATAPATH_TBUS_BRIDGE_WINDOW_UPPER; // RW  32 bits
.CONST $SQIF_DATAPATH_TBUS_BRIDGE_REMOTE_SS_ID 0xFFFF966C; // RW   4 bits
.CONST $_SQIF_DATAPATH_TBUS_BRIDGE_REMOTE_SS_ID $SQIF_DATAPATH_TBUS_BRIDGE_REMOTE_SS_ID; // RW   4 bits
.CONST $SQIF_DATAPATH_TBUS_BRIDGE_REMOTE_BLOCK_ID 0xFFFF9670; // RW   4 bits
.CONST $_SQIF_DATAPATH_TBUS_BRIDGE_REMOTE_BLOCK_ID $SQIF_DATAPATH_TBUS_BRIDGE_REMOTE_BLOCK_ID; // RW   4 bits
.CONST $SQIF_DATAPATH_TBUS_BRIDGE_REMOTE_ADDR_OFFSET 0xFFFF9674; // RW  32 bits
.CONST $_SQIF_DATAPATH_TBUS_BRIDGE_REMOTE_ADDR_OFFSET $SQIF_DATAPATH_TBUS_BRIDGE_REMOTE_ADDR_OFFSET; // RW  32 bits
.CONST $SQIF_DATAPATH_TBUS_BRIDGE_REMOTE_CONFIG 0xFFFF9678; // RW   1 bits
.CONST $_SQIF_DATAPATH_TBUS_BRIDGE_REMOTE_CONFIG $SQIF_DATAPATH_TBUS_BRIDGE_REMOTE_CONFIG; // RW   1 bits
.CONST $SQIF_DATAPATH_TBUS_BRIDGE_REMOTE_DATA_LSW 0xFFFF967C; //  R  32 bits
.CONST $_SQIF_DATAPATH_TBUS_BRIDGE_REMOTE_DATA_LSW $SQIF_DATAPATH_TBUS_BRIDGE_REMOTE_DATA_LSW; //  R  32 bits
.CONST $SQIF_DATAPATH_TBUS_BRIDGE_REMOTE_DATA_MSW 0xFFFF9680; //  R  32 bits
.CONST $_SQIF_DATAPATH_TBUS_BRIDGE_REMOTE_DATA_MSW $SQIF_DATAPATH_TBUS_BRIDGE_REMOTE_DATA_MSW; //  R  32 bits
.CONST $SQIF_DATAPATH_TBUS_BRIDGE_REMOTE_CONTROL 0xFFFF9684; // RW  10 bits
.CONST $_SQIF_DATAPATH_TBUS_BRIDGE_REMOTE_CONTROL $SQIF_DATAPATH_TBUS_BRIDGE_REMOTE_CONTROL; // RW  10 bits
.CONST $SQIF_DATAPATH_TBUS_BRIDGE_REMOTE_STATUS 0xFFFF9688; //  R   6 bits
.CONST $_SQIF_DATAPATH_TBUS_BRIDGE_REMOTE_STATUS $SQIF_DATAPATH_TBUS_BRIDGE_REMOTE_STATUS; //  R   6 bits
.CONST $SQIF_DATAPATH_TBUS_BRIDGE_MUTEX_LOCK 0xFFFF968C; // RW   4 bits
.CONST $_SQIF_DATAPATH_TBUS_BRIDGE_MUTEX_LOCK $SQIF_DATAPATH_TBUS_BRIDGE_MUTEX_LOCK; // RW   4 bits
.CONST $SQIF_DATAPATH_TBUS_BRIDGE_ACCESS_CTRL 0xFFFF9690; // RW   4 bits
.CONST $_SQIF_DATAPATH_TBUS_BRIDGE_ACCESS_CTRL $SQIF_DATAPATH_TBUS_BRIDGE_ACCESS_CTRL; // RW   4 bits
.CONST $SQIF_DATAPATH_PORT_STATUS            0xFFFF9694; // RW   1 bits
.CONST $_SQIF_DATAPATH_PORT_STATUS           $SQIF_DATAPATH_PORT_STATUS; // RW   1 bits
.CONST $SQIF_DATAPATH_PERF_COUNTER           0xFFFF9698; //  R  32 bits
.CONST $_SQIF_DATAPATH_PERF_COUNTER          $SQIF_DATAPATH_PERF_COUNTER; //  R  32 bits
.CONST $SQIF_INST                            0xFFFF96A0; // RW  16 bits
.CONST $_SQIF_INST                           $SQIF_INST; // RW  16 bits
.CONST $SQIF_CONF                            0xFFFF96A4; // RW  12 bits
.CONST $_SQIF_CONF                           $SQIF_CONF; // RW  12 bits
.CONST $SQIF_CONF2                           0xFFFF96A8; // RW  13 bits
.CONST $_SQIF_CONF2                          $SQIF_CONF2; // RW  13 bits
.CONST $SQIF_CTRL                            0xFFFF96AC; // RW  12 bits
.CONST $_SQIF_CTRL                           $SQIF_CTRL; // RW  12 bits
.CONST $SQIF_PEEK                            0xFFFF96B0; //  R   8 bits
.CONST $_SQIF_PEEK                           $SQIF_PEEK; //  R   8 bits
.CONST $SQIF_PEEK_GO                         0xFFFF96B4; // RW   1 bits
.CONST $_SQIF_PEEK_GO                        $SQIF_PEEK_GO; // RW   1 bits
.CONST $SQIF_POKE                            0xFFFF96B8; // RW   8 bits
.CONST $_SQIF_POKE                           $SQIF_POKE; // RW   8 bits
.CONST $SQIF_POKE_LAST                       0xFFFF96BC; // RW   8 bits
.CONST $_SQIF_POKE_LAST                      $SQIF_POKE_LAST; // RW   8 bits
.CONST $SQIF_PHASE_SEL0                      0xFFFF96C4; // RW  15 bits
.CONST $_SQIF_PHASE_SEL0                     $SQIF_PHASE_SEL0; // RW  15 bits
.CONST $SQIF_PHASE_SEL1                      0xFFFF96C8; // RW  15 bits
.CONST $_SQIF_PHASE_SEL1                     $SQIF_PHASE_SEL1; // RW  15 bits
.CONST $SQIF_PHASE_SEL2                      0xFFFF96CC; // RW  11 bits
.CONST $_SQIF_PHASE_SEL2                     $SQIF_PHASE_SEL2; // RW  11 bits
.CONST $SQIF_DDR_DBG_SEL                     0xFFFF96D0; // RW   8 bits
.CONST $_SQIF_DDR_DBG_SEL                    $SQIF_DDR_DBG_SEL; // RW   8 bits
.CONST $SQIF_DDR_MARGIN                      0xFFFF96D4; //  R  10 bits
.CONST $_SQIF_DDR_MARGIN                     $SQIF_DDR_MARGIN; //  R  10 bits
.CONST $SQIF_DEBUG_SEL                       0xFFFF96D8; // RW   4 bits
.CONST $_SQIF_DEBUG_SEL                      $SQIF_DEBUG_SEL; // RW   4 bits
.CONST $SQIF_FLASH_SIZE                      0xFFFF96DC; // RW   6 bits
.CONST $_SQIF_FLASH_SIZE                     $SQIF_FLASH_SIZE; // RW   6 bits
.CONST $SQIF_MUTEX_LOCK                      0xFFFF96E0; // RW   4 bits
.CONST $_SQIF_MUTEX_LOCK                     $SQIF_MUTEX_LOCK; // RW   4 bits
.CONST $SQIF_ACCESS_CTRL                     0xFFFF96E4; // RW   4 bits
.CONST $_SQIF_ACCESS_CTRL                    $SQIF_ACCESS_CTRL; // RW   4 bits
.CONST $SQIF_PAD_CAL                         0xFFFF96E8; // RW   5 bits
.CONST $_SQIF_PAD_CAL                        $SQIF_PAD_CAL; // RW   5 bits
.CONST $SQIF_RAM_CONF                        0xFFFF96EC; // RW   8 bits
.CONST $_SQIF_RAM_CONF                       $SQIF_RAM_CONF; // RW   8 bits
.CONST $SQIF_CORR_CFG                        0xFFFF96F0; // RW  14 bits
.CONST $_SQIF_CORR_CFG                       $SQIF_CORR_CFG; // RW  14 bits
.CONST $SQIF_DDR_LOCKED                      0xFFFF96F4; //  R   4 bits
.CONST $_SQIF_DDR_LOCKED                     $SQIF_DDR_LOCKED; //  R   4 bits
.CONST $SQIF_DDR_CENTER                      0xFFFF96F8; //  R  10 bits
.CONST $_SQIF_DDR_CENTER                     $SQIF_DDR_CENTER; //  R  10 bits
.CONST $SQIF_PAD_DBG                         0xFFFF96FC; //  R   6 bits
.CONST $_SQIF_PAD_DBG                        $SQIF_PAD_DBG; //  R   6 bits
.CONST $REMOTE_SUBSYSTEM_ACCESS_REG_BASED_ACCESS_ADDR 0xFFFF9700; // RW  32 bits
.CONST $_REMOTE_SUBSYSTEM_ACCESS_REG_BASED_ACCESS_ADDR $REMOTE_SUBSYSTEM_ACCESS_REG_BASED_ACCESS_ADDR; // RW  32 bits
.CONST $REMOTE_SUBSYSTEM_ACCESS_REG_BASED_ACCESS_WRITE_DATA 0xFFFF9704; // RW  32 bits
.CONST $_REMOTE_SUBSYSTEM_ACCESS_REG_BASED_ACCESS_WRITE_DATA $REMOTE_SUBSYSTEM_ACCESS_REG_BASED_ACCESS_WRITE_DATA; // RW  32 bits
.CONST $REMOTE_SUBSYSTEM_ACCESS_REG_BASED_ACCESS_READ_DATA 0xFFFF9708; //  R  32 bits
.CONST $_REMOTE_SUBSYSTEM_ACCESS_REG_BASED_ACCESS_READ_DATA $REMOTE_SUBSYSTEM_ACCESS_REG_BASED_ACCESS_READ_DATA; //  R  32 bits
.CONST $REMOTE_SUBSYSTEM_ACCESS_REG_BASED_ACCESS_CTRL 0xFFFF970C; // RW  13 bits
.CONST $_REMOTE_SUBSYSTEM_ACCESS_REG_BASED_ACCESS_CTRL $REMOTE_SUBSYSTEM_ACCESS_REG_BASED_ACCESS_CTRL; // RW  13 bits
.CONST $REMOTE_SUBSYSTEM_ACCESS_REG_BASED_ACCESS_TRIG 0xFFFF9718; // RW   1 bits
.CONST $_REMOTE_SUBSYSTEM_ACCESS_REG_BASED_ACCESS_TRIG $REMOTE_SUBSYSTEM_ACCESS_REG_BASED_ACCESS_TRIG; // RW   1 bits
.CONST $REMOTE_SUBSYSTEM_ACCESS_REG_BASED_CONFIG 0xFFFF971C; // RW   3 bits
.CONST $_REMOTE_SUBSYSTEM_ACCESS_REG_BASED_CONFIG $REMOTE_SUBSYSTEM_ACCESS_REG_BASED_CONFIG; // RW   3 bits
.CONST $REMOTE_SUBSYSTEM_ACCESS_REG_BASED_STATUS 0xFFFF9720; //  R   5 bits
.CONST $_REMOTE_SUBSYSTEM_ACCESS_REG_BASED_STATUS $REMOTE_SUBSYSTEM_ACCESS_REG_BASED_STATUS; //  R   5 bits
.CONST $REMOTE_SUBSYSTEM_ACCESS_REG_BASED_STATUS_CLEAR 0xFFFF9724; // RW   1 bits
.CONST $_REMOTE_SUBSYSTEM_ACCESS_REG_BASED_STATUS_CLEAR $REMOTE_SUBSYSTEM_ACCESS_REG_BASED_STATUS_CLEAR; // RW   1 bits
.CONST $REMOTE_SUBSYSTEM_ACCESS_WINDOW0_CONFIG 0xFFFF9728; // RW  12 bits
.CONST $_REMOTE_SUBSYSTEM_ACCESS_WINDOW0_CONFIG $REMOTE_SUBSYSTEM_ACCESS_WINDOW0_CONFIG; // RW  12 bits
.CONST $REMOTE_SUBSYSTEM_ACCESS_WINDOW0_STATUS 0xFFFF972C; //  R   5 bits
.CONST $_REMOTE_SUBSYSTEM_ACCESS_WINDOW0_STATUS $REMOTE_SUBSYSTEM_ACCESS_WINDOW0_STATUS; //  R   5 bits
.CONST $REMOTE_SUBSYSTEM_ACCESS_WINDOW0_STATUS_CLEAR 0xFFFF9730; // RW   1 bits
.CONST $_REMOTE_SUBSYSTEM_ACCESS_WINDOW0_STATUS_CLEAR $REMOTE_SUBSYSTEM_ACCESS_WINDOW0_STATUS_CLEAR; // RW   1 bits
.CONST $REMOTE_SUBSYSTEM_ACCESS_WINDOW1_CONFIG 0xFFFF9734; // RW  12 bits
.CONST $_REMOTE_SUBSYSTEM_ACCESS_WINDOW1_CONFIG $REMOTE_SUBSYSTEM_ACCESS_WINDOW1_CONFIG; // RW  12 bits
.CONST $REMOTE_SUBSYSTEM_ACCESS_WINDOW1_STATUS 0xFFFF9738; //  R   5 bits
.CONST $_REMOTE_SUBSYSTEM_ACCESS_WINDOW1_STATUS $REMOTE_SUBSYSTEM_ACCESS_WINDOW1_STATUS; //  R   5 bits
.CONST $REMOTE_SUBSYSTEM_ACCESS_WINDOW1_STATUS_CLEAR 0xFFFF973C; // RW   1 bits
.CONST $_REMOTE_SUBSYSTEM_ACCESS_WINDOW1_STATUS_CLEAR $REMOTE_SUBSYSTEM_ACCESS_WINDOW1_STATUS_CLEAR; // RW   1 bits
.CONST $REMOTE_SUBSYSTEM_ACCESS_REM_REGS_WINDOW_CONFIG 0xFFFF9740; // RW   2 bits
.CONST $_REMOTE_SUBSYSTEM_ACCESS_REM_REGS_WINDOW_CONFIG $REMOTE_SUBSYSTEM_ACCESS_REM_REGS_WINDOW_CONFIG; // RW   2 bits
.CONST $REMOTE_SUBSYSTEM_ACCESS_REM_REGS_WINDOW_STATUS 0xFFFF9744; //  R   5 bits
.CONST $_REMOTE_SUBSYSTEM_ACCESS_REM_REGS_WINDOW_STATUS $REMOTE_SUBSYSTEM_ACCESS_REM_REGS_WINDOW_STATUS; //  R   5 bits
.CONST $REMOTE_SUBSYSTEM_ACCESS_REM_REGS_WINDOW_STATUS_CLEAR 0xFFFF9748; // RW   1 bits
.CONST $_REMOTE_SUBSYSTEM_ACCESS_REM_REGS_WINDOW_STATUS_CLEAR $REMOTE_SUBSYSTEM_ACCESS_REM_REGS_WINDOW_STATUS_CLEAR; // RW   1 bits
.CONST $REMOTE_SUBSYSTEM_ACCESS_MUTEX_LOCK   0xFFFF974C; // RW   4 bits
.CONST $_REMOTE_SUBSYSTEM_ACCESS_MUTEX_LOCK  $REMOTE_SUBSYSTEM_ACCESS_MUTEX_LOCK; // RW   4 bits
.CONST $REMOTE_SUBSYSTEM_ACCESS_ACCESS_CTRL  0xFFFF9750; // RW   4 bits
.CONST $_REMOTE_SUBSYSTEM_ACCESS_ACCESS_CTRL $REMOTE_SUBSYSTEM_ACCESS_ACCESS_CTRL; // RW   4 bits
.CONST $REMOTE_SUBSYSTEM_ACCESS_MISC         0xFFFF9754; // RW  10 bits
.CONST $_REMOTE_SUBSYSTEM_ACCESS_MISC        $REMOTE_SUBSYSTEM_ACCESS_MISC; // RW  10 bits
.CONST $BUS_PROC_STREAM_PAYLOAD0             0xFFFF9760; // RW  32 bits
.CONST $_BUS_PROC_STREAM_PAYLOAD0            $BUS_PROC_STREAM_PAYLOAD0; // RW  32 bits
.CONST $BUS_PROC_STREAM_PAYLOAD1             0xFFFF9764; // RW  32 bits
.CONST $_BUS_PROC_STREAM_PAYLOAD1            $BUS_PROC_STREAM_PAYLOAD1; // RW  32 bits
.CONST $BUS_PROC_STREAM_FINAL                0xFFFF9768; // RW  16 bits
.CONST $_BUS_PROC_STREAM_FINAL               $BUS_PROC_STREAM_FINAL; // RW  16 bits
.CONST $BUS_PROC_STREAM_CONFIG               0xFFFF976C; // RW  12 bits
.CONST $_BUS_PROC_STREAM_CONFIG              $BUS_PROC_STREAM_CONFIG; // RW  12 bits
.CONST $BUS_PROC_STREAM_MUTEX_LOCK           0xFFFF9770; // RW   4 bits
.CONST $_BUS_PROC_STREAM_MUTEX_LOCK          $BUS_PROC_STREAM_MUTEX_LOCK; // RW   4 bits
.CONST $BUS_PROC_STREAM_ACCESS_CTRL          0xFFFF9774; // RW   4 bits
.CONST $_BUS_PROC_STREAM_ACCESS_CTRL         $BUS_PROC_STREAM_ACCESS_CTRL; // RW   4 bits
.CONST $TRACE_0_CFG                          0xFFFF97C0; // RW  10 bits
.CONST $_TRACE_0_CFG                         $TRACE_0_CFG; // RW  10 bits
.CONST $TRACE_0_TRIGGER_CFG                  0xFFFF97C4; // RW  12 bits
.CONST $_TRACE_0_TRIGGER_CFG                 $TRACE_0_TRIGGER_CFG; // RW  12 bits
.CONST $TRACE_0_START_TRIGGER                0xFFFF97C8; // RW  32 bits
.CONST $_TRACE_0_START_TRIGGER               $TRACE_0_START_TRIGGER; // RW  32 bits
.CONST $TRACE_0_END_TRIGGER                  0xFFFF97CC; // RW  32 bits
.CONST $_TRACE_0_END_TRIGGER                 $TRACE_0_END_TRIGGER; // RW  32 bits
.CONST $TRACE_0_TBUS_CFG                     0xFFFF97D0; // RW  30 bits
.CONST $_TRACE_0_TBUS_CFG                    $TRACE_0_TBUS_CFG; // RW  30 bits
.CONST $TRACE_0_TBUS_BASE_ADDR               0xFFFF97D4; // RW  32 bits
.CONST $_TRACE_0_TBUS_BASE_ADDR              $TRACE_0_TBUS_BASE_ADDR; // RW  32 bits
.CONST $TRACE_0_DMEM_CFG                     0xFFFF97D8; // RW  13 bits
.CONST $_TRACE_0_DMEM_CFG                    $TRACE_0_DMEM_CFG; // RW  13 bits
.CONST $TRACE_0_DMEM_BASE_ADDR               0xFFFF97DC; // RW  32 bits
.CONST $_TRACE_0_DMEM_BASE_ADDR              $TRACE_0_DMEM_BASE_ADDR; // RW  32 bits
.CONST $TRACE_1_CFG                          0xFFFF97E0; // RW  10 bits
.CONST $_TRACE_1_CFG                         $TRACE_1_CFG; // RW  10 bits
.CONST $TRACE_1_TRIGGER_CFG                  0xFFFF97E4; // RW  12 bits
.CONST $_TRACE_1_TRIGGER_CFG                 $TRACE_1_TRIGGER_CFG; // RW  12 bits
.CONST $TRACE_1_START_TRIGGER                0xFFFF97E8; // RW  32 bits
.CONST $_TRACE_1_START_TRIGGER               $TRACE_1_START_TRIGGER; // RW  32 bits
.CONST $TRACE_1_END_TRIGGER                  0xFFFF97EC; // RW  32 bits
.CONST $_TRACE_1_END_TRIGGER                 $TRACE_1_END_TRIGGER; // RW  32 bits
.CONST $TRACE_1_TBUS_CFG                     0xFFFF97F0; // RW  30 bits
.CONST $_TRACE_1_TBUS_CFG                    $TRACE_1_TBUS_CFG; // RW  30 bits
.CONST $TRACE_1_TBUS_BASE_ADDR               0xFFFF97F4; // RW  32 bits
.CONST $_TRACE_1_TBUS_BASE_ADDR              $TRACE_1_TBUS_BASE_ADDR; // RW  32 bits
.CONST $TRACE_1_DMEM_CFG                     0xFFFF97F8; // RW  13 bits
.CONST $_TRACE_1_DMEM_CFG                    $TRACE_1_DMEM_CFG; // RW  13 bits
.CONST $TRACE_1_DMEM_BASE_ADDR               0xFFFF97FC; // RW  32 bits
.CONST $_TRACE_1_DMEM_BASE_ADDR              $TRACE_1_DMEM_BASE_ADDR; // RW  32 bits
.CONST $TRACE_TBUS_STATUS                    0xFFFF9800; //  R   4 bits
.CONST $_TRACE_TBUS_STATUS                   $TRACE_TBUS_STATUS; //  R   4 bits
.CONST $TRACE_DMEM_STATUS                    0xFFFF9804; //  R   4 bits
.CONST $_TRACE_DMEM_STATUS                   $TRACE_DMEM_STATUS; //  R   4 bits
.CONST $TRACE_MUTEX_LOCK                     0xFFFF9808; // RW   4 bits
.CONST $_TRACE_MUTEX_LOCK                    $TRACE_MUTEX_LOCK; // RW   4 bits
.CONST $TRACE_ACCESS_CTRL                    0xFFFF980C; // RW   4 bits
.CONST $_TRACE_ACCESS_CTRL                   $TRACE_ACCESS_CTRL; // RW   4 bits
.CONST $TRACE_0_TRIGGER_STATUS               0xFFFF9810; //  R   6 bits
.CONST $_TRACE_0_TRIGGER_STATUS              $TRACE_0_TRIGGER_STATUS; //  R   6 bits
.CONST $TRACE_1_TRIGGER_STATUS               0xFFFF9814; //  R   6 bits
.CONST $_TRACE_1_TRIGGER_STATUS              $TRACE_1_TRIGGER_STATUS; //  R   6 bits
.CONST $TRACE_DEBUG_SEL                      0xFFFF9818; // RW   4 bits
.CONST $_TRACE_DEBUG_SEL                     $TRACE_DEBUG_SEL; // RW   4 bits
.CONST $APPS_REMOTE_SUBSYSTEM_ACCESSOR_ACCESS_CONTROL 0xFFFF98A4; // RW   4 bits
.CONST $_APPS_REMOTE_SUBSYSTEM_ACCESSOR_ACCESS_CONTROL $APPS_REMOTE_SUBSYSTEM_ACCESSOR_ACCESS_CONTROL; // RW   4 bits
.CONST $APPS_SYS_INTERCONNECT_DEBUG_CONTROL  0xFFFF98A8; // RW  15 bits
.CONST $_APPS_SYS_INTERCONNECT_DEBUG_CONTROL $APPS_SYS_INTERCONNECT_DEBUG_CONTROL; // RW  15 bits
.CONST $APPS_SYS_DM0_ACCESS_RESTRICT         0xFFFF98AC; // RW   2 bits
.CONST $_APPS_SYS_DM0_ACCESS_RESTRICT        $APPS_SYS_DM0_ACCESS_RESTRICT; // RW   2 bits
.CONST $APPS_BANKED_TBUS_INT_P0_STATUS       0xFFFF9990; // RW  16 bits
.CONST $_APPS_BANKED_TBUS_INT_P0_STATUS      $APPS_BANKED_TBUS_INT_P0_STATUS; // RW  16 bits
.CONST $APPS_BANKED_TBUS_INT_P0_ENABLES      0xFFFF9994; // RW  16 bits
.CONST $_APPS_BANKED_TBUS_INT_P0_ENABLES     $APPS_BANKED_TBUS_INT_P0_ENABLES; // RW  16 bits
.CONST $APPS_BANKED_TBUS_INT_P0_MUTEX_LOCK   0xFFFF9998; // RW   4 bits
.CONST $_APPS_BANKED_TBUS_INT_P0_MUTEX_LOCK  $APPS_BANKED_TBUS_INT_P0_MUTEX_LOCK; // RW   4 bits
.CONST $APPS_BANKED_TBUS_INT_P0_ACCESS_CTRL  0xFFFF999C; // RW   4 bits
.CONST $_APPS_BANKED_TBUS_INT_P0_ACCESS_CTRL $APPS_BANKED_TBUS_INT_P0_ACCESS_CTRL; // RW   4 bits
.CONST $APPS_BANKED_EXCEPTIONS_P0_STATUS     0xFFFF99B0; // RW  20 bits
.CONST $_APPS_BANKED_EXCEPTIONS_P0_STATUS    $APPS_BANKED_EXCEPTIONS_P0_STATUS; // RW  20 bits
.CONST $APPS_BANKED_EXCEPTIONS_P0_ENABLES    0xFFFF99B4; // RW  20 bits
.CONST $_APPS_BANKED_EXCEPTIONS_P0_ENABLES   $APPS_BANKED_EXCEPTIONS_P0_ENABLES; // RW  20 bits
.CONST $APPS_BANKED_EXCEPTIONS_P0_MUTEX_LOCK 0xFFFF99B8; // RW   4 bits
.CONST $_APPS_BANKED_EXCEPTIONS_P0_MUTEX_LOCK $APPS_BANKED_EXCEPTIONS_P0_MUTEX_LOCK; // RW   4 bits
.CONST $APPS_BANKED_EXCEPTIONS_P0_ACCESS_CTRL 0xFFFF99BC; // RW   4 bits
.CONST $_APPS_BANKED_EXCEPTIONS_P0_ACCESS_CTRL $APPS_BANKED_EXCEPTIONS_P0_ACCESS_CTRL; // RW   4 bits
.CONST $APPS_BANKED_EXCEPTIONS_P1_STATUS     0xFFFF99C0; // RW  20 bits
.CONST $_APPS_BANKED_EXCEPTIONS_P1_STATUS    $APPS_BANKED_EXCEPTIONS_P1_STATUS; // RW  20 bits
.CONST $APPS_BANKED_EXCEPTIONS_P1_ENABLES    0xFFFF99C4; // RW  20 bits
.CONST $_APPS_BANKED_EXCEPTIONS_P1_ENABLES   $APPS_BANKED_EXCEPTIONS_P1_ENABLES; // RW  20 bits
.CONST $APPS_BANKED_EXCEPTIONS_P1_MUTEX_LOCK 0xFFFF99C8; // RW   4 bits
.CONST $_APPS_BANKED_EXCEPTIONS_P1_MUTEX_LOCK $APPS_BANKED_EXCEPTIONS_P1_MUTEX_LOCK; // RW   4 bits
.CONST $APPS_BANKED_EXCEPTIONS_P1_ACCESS_CTRL 0xFFFF99CC; // RW   4 bits
.CONST $_APPS_BANKED_EXCEPTIONS_P1_ACCESS_CTRL $APPS_BANKED_EXCEPTIONS_P1_ACCESS_CTRL; // RW   4 bits
.CONST $APPS_SYS_SQIF0_PRESENT               0xFFFF99E0; // RW   2 bits
.CONST $_APPS_SYS_SQIF0_PRESENT              $APPS_SYS_SQIF0_PRESENT; // RW   2 bits
.CONST $APPS_SYS_SQIF1_PRESENT               0xFFFF99E4; // RW   2 bits
.CONST $_APPS_SYS_SQIF1_PRESENT              $APPS_SYS_SQIF1_PRESENT; // RW   2 bits
.CONST $SEMAPHORE_DATA                       0xFFFF99F0; // RW   1 bits
.CONST $_SEMAPHORE_DATA                      $SEMAPHORE_DATA; // RW   1 bits
.CONST $SEMAPHORE_ADDR                       0xFFFF99F4; // RW   6 bits
.CONST $_SEMAPHORE_ADDR                      $SEMAPHORE_ADDR; // RW   6 bits
.CONST $SEMAPHORE_STATUS                     0xFFFF99F8; //  R   1 bits
.CONST $_SEMAPHORE_STATUS                    $SEMAPHORE_STATUS; //  R   1 bits
.CONST $SEMAPHORE_STATUS_RAW                 0xFFFF99FC; //  R   1 bits
.CONST $_SEMAPHORE_STATUS_RAW                $SEMAPHORE_STATUS_RAW; //  R   1 bits
.CONST $VM_FREE_LIST_ADDR                    0xFFFF9A00; // RW  32 bits
.CONST $_VM_FREE_LIST_ADDR                   $VM_FREE_LIST_ADDR; // RW  32 bits
.CONST $VM_FREE_LIST_END_ADDR                0xFFFF9A04; // RW  32 bits
.CONST $_VM_FREE_LIST_END_ADDR               $VM_FREE_LIST_END_ADDR; // RW  32 bits
.CONST $VM_FREE_LIST_ADD_PAGE                0xFFFF9A08; // RW  16 bits
.CONST $_VM_FREE_LIST_ADD_PAGE               $VM_FREE_LIST_ADD_PAGE; // RW  16 bits
.CONST $VM_DEBUG_SELECT                      0xFFFF9A0C; // RW   5 bits
.CONST $_VM_DEBUG_SELECT                     $VM_DEBUG_SELECT; // RW   5 bits
.CONST $VM_REQUEST_CPU0_WRITE_REMOTE_CONFIG  0xFFFF9A10; // RW  14 bits
.CONST $_VM_REQUEST_CPU0_WRITE_REMOTE_CONFIG $VM_REQUEST_CPU0_WRITE_REMOTE_CONFIG; // RW  14 bits
.CONST $VM_REQUEST_CPU0_READ_REMOTE_CONFIG   0xFFFF9A14; // RW  14 bits
.CONST $_VM_REQUEST_CPU0_READ_REMOTE_CONFIG  $VM_REQUEST_CPU0_READ_REMOTE_CONFIG; // RW  14 bits
.CONST $VM_REQUEST_CPU1_REQUESTS_REMOTE_CONFIG_DENIED_STATUS_CLEAR 0xFFFF9A18; //  W   1 bits
.CONST $_VM_REQUEST_CPU1_REQUESTS_REMOTE_CONFIG_DENIED_STATUS_CLEAR $VM_REQUEST_CPU1_REQUESTS_REMOTE_CONFIG_DENIED_STATUS_CLEAR; //  W   1 bits
.CONST $VM_LOOKUP_SELECT                     0xFFFF9A20; // RW   4 bits
.CONST $_VM_LOOKUP_SELECT                    $VM_LOOKUP_SELECT; // RW   4 bits
.CONST $VM_LOOKUP_ERROR_FLAGS                0xFFFF9A24; //  R  16 bits
.CONST $_VM_LOOKUP_ERROR_FLAGS               $VM_LOOKUP_ERROR_FLAGS; //  R  16 bits
.CONST $VM_LOOKUP_ERROR_FLAGS_CLEAR          0xFFFF9A28; // RW  16 bits
.CONST $_VM_LOOKUP_ERROR_FLAGS_CLEAR         $VM_LOOKUP_ERROR_FLAGS_CLEAR; // RW  16 bits
.CONST $VM_LOOKUP_INT_EVENTS_STICKY          0xFFFF9A2C; //  R  16 bits
.CONST $_VM_LOOKUP_INT_EVENTS_STICKY         $VM_LOOKUP_INT_EVENTS_STICKY; //  R  16 bits
.CONST $VM_CPU0_CLEAR_PORT                   0xFFFF9A30; // RW   2 bits
.CONST $_VM_CPU0_CLEAR_PORT                  $VM_CPU0_CLEAR_PORT; // RW   2 bits
.CONST $VM_REQUEST_CPU0_WRITE_STATUS         0xFFFF9A38; //  R  18 bits
.CONST $_VM_REQUEST_CPU0_WRITE_STATUS        $VM_REQUEST_CPU0_WRITE_STATUS; //  R  18 bits
.CONST $VM_REQUEST_CPU0_READ_STATUS          0xFFFF9A3C; //  R  18 bits
.CONST $_VM_REQUEST_CPU0_READ_STATUS         $VM_REQUEST_CPU0_READ_STATUS; //  R  18 bits
.CONST $VM_REQUEST_CPU1_WRITE_STATUS         0xFFFF9A40; //  R  18 bits
.CONST $_VM_REQUEST_CPU1_WRITE_STATUS        $VM_REQUEST_CPU1_WRITE_STATUS; //  R  18 bits
.CONST $VM_REQUEST_CPU1_READ_STATUS          0xFFFF9A44; //  R  18 bits
.CONST $_VM_REQUEST_CPU1_READ_STATUS         $VM_REQUEST_CPU1_READ_STATUS; //  R  18 bits
.CONST $VM_FREE_LIST_NEXT_ADDR               0xFFFF9A50; //  R  32 bits
.CONST $_VM_FREE_LIST_NEXT_ADDR              $VM_FREE_LIST_NEXT_ADDR; //  R  32 bits
.CONST $VM_BUFFER_ACCESS_CPU0_HANDLE         0xFFFF9A54; // RW  12 bits
.CONST $_VM_BUFFER_ACCESS_CPU0_HANDLE        $VM_BUFFER_ACCESS_CPU0_HANDLE; // RW  12 bits
.CONST $VM_BUFFER_ACCESS_CPU0_OFFSET_WRITE   0xFFFF9A58; // RW  18 bits
.CONST $_VM_BUFFER_ACCESS_CPU0_OFFSET_WRITE  $VM_BUFFER_ACCESS_CPU0_OFFSET_WRITE; // RW  18 bits
.CONST $VM_BUFFER_ACCESS_CPU0_DO_ACTION      0xFFFF9A5C; // RW   1 bits
.CONST $_VM_BUFFER_ACCESS_CPU0_DO_ACTION     $VM_BUFFER_ACCESS_CPU0_DO_ACTION; // RW   1 bits
.CONST $VM_BUFFER_ACCESS_CPU0_STATUS         0xFFFF9A60; //  R   5 bits
.CONST $_VM_BUFFER_ACCESS_CPU0_STATUS        $VM_BUFFER_ACCESS_CPU0_STATUS; //  R   5 bits
.CONST $VM_BUFFER_ACCESS_CPU0_OFFSET_READ    0xFFFF9A64; //  R  18 bits
.CONST $_VM_BUFFER_ACCESS_CPU0_OFFSET_READ   $VM_BUFFER_ACCESS_CPU0_OFFSET_READ; //  R  18 bits
.CONST $VM_BUFFER_ACCESS_CPU1_HANDLE         0xFFFF9A68; // RW  12 bits
.CONST $_VM_BUFFER_ACCESS_CPU1_HANDLE        $VM_BUFFER_ACCESS_CPU1_HANDLE; // RW  12 bits
.CONST $VM_BUFFER_ACCESS_CPU1_OFFSET_WRITE   0xFFFF9A6C; // RW  18 bits
.CONST $_VM_BUFFER_ACCESS_CPU1_OFFSET_WRITE  $VM_BUFFER_ACCESS_CPU1_OFFSET_WRITE; // RW  18 bits
.CONST $VM_BUFFER_ACCESS_CPU1_DO_ACTION      0xFFFF9A70; // RW   1 bits
.CONST $_VM_BUFFER_ACCESS_CPU1_DO_ACTION     $VM_BUFFER_ACCESS_CPU1_DO_ACTION; // RW   1 bits
.CONST $VM_BUFFER_ACCESS_CPU1_STATUS         0xFFFF9A74; //  R   5 bits
.CONST $_VM_BUFFER_ACCESS_CPU1_STATUS        $VM_BUFFER_ACCESS_CPU1_STATUS; //  R   5 bits
.CONST $VM_BUFFER_ACCESS_CPU1_OFFSET_READ    0xFFFF9A78; //  R  18 bits
.CONST $_VM_BUFFER_ACCESS_CPU1_OFFSET_READ   $VM_BUFFER_ACCESS_CPU1_OFFSET_READ; //  R  18 bits
.CONST $VM_CPU0_MUTEX_LOCK                   0xFFFF9A7C; // RW   4 bits
.CONST $_VM_CPU0_MUTEX_LOCK                  $VM_CPU0_MUTEX_LOCK; // RW   4 bits
.CONST $VM_CPU0_ACCESS_CTRL                  0xFFFF9A80; // RW   4 bits
.CONST $_VM_CPU0_ACCESS_CTRL                 $VM_CPU0_ACCESS_CTRL; // RW   4 bits
.CONST $VM_LOOKUP_ALLOW_READING_FROM_UNMAPPED_PAGES 0xFFFF9A84; // RW   1 bits
.CONST $_VM_LOOKUP_ALLOW_READING_FROM_UNMAPPED_PAGES $VM_LOOKUP_ALLOW_READING_FROM_UNMAPPED_PAGES; // RW   1 bits
.CONST $VM_CPU1_CLEAR_PORT                   0xFFFF9A88; // RW   2 bits
.CONST $_VM_CPU1_CLEAR_PORT                  $VM_CPU1_CLEAR_PORT; // RW   2 bits
.CONST $VM_CPU1_MUTEX_LOCK                   0xFFFF9A90; // RW   4 bits
.CONST $_VM_CPU1_MUTEX_LOCK                  $VM_CPU1_MUTEX_LOCK; // RW   4 bits
.CONST $VM_CPU1_ACCESS_CTRL                  0xFFFF9A94; // RW   4 bits
.CONST $_VM_CPU1_ACCESS_CTRL                 $VM_CPU1_ACCESS_CTRL; // RW   4 bits
.CONST $APPS_SYS_APU_CONTROL                 0xFFFF9AC0; // RW   3 bits
.CONST $_APPS_SYS_APU_CONTROL                $APPS_SYS_APU_CONTROL; // RW   3 bits
.CONST $APPS_SYS_APU_STATUS                  0xFFFF9AC4; //  R   9 bits
.CONST $_APPS_SYS_APU_STATUS                 $APPS_SYS_APU_STATUS; //  R   9 bits
.CONST $APPS_SYS_APU_AREA_SELECT             0xFFFF9AC8; // RW   5 bits
.CONST $_APPS_SYS_APU_AREA_SELECT            $APPS_SYS_APU_AREA_SELECT; // RW   5 bits
.CONST $APPS_SYS_APU_FAULT_ADDRESS           0xFFFF9ACC; //  R  32 bits
.CONST $_APPS_SYS_APU_FAULT_ADDRESS          $APPS_SYS_APU_FAULT_ADDRESS; //  R  32 bits
.CONST $APPS_SYS_APU_FAULT_DATA              0xFFFF9AD0; // RW  32 bits
.CONST $_APPS_SYS_APU_FAULT_DATA             $APPS_SYS_APU_FAULT_DATA; // RW  32 bits
.CONST $APPS_SYS_APU_AREA_CONTROL            0xFFFF9AD4; // RW   3 bits
.CONST $_APPS_SYS_APU_AREA_CONTROL           $APPS_SYS_APU_AREA_CONTROL; // RW   3 bits
.CONST $APPS_SYS_APU_FAULT_RELEASE_CLEAR     0xFFFF9AD8; //  W   1 bits
.CONST $_APPS_SYS_APU_FAULT_RELEASE_CLEAR    $APPS_SYS_APU_FAULT_RELEASE_CLEAR; //  W   1 bits
.CONST $APPS_SYS_APU_AREA_WINDOW_LO          0xFFFF9ADC; // RW  32 bits
.CONST $_APPS_SYS_APU_AREA_WINDOW_LO         $APPS_SYS_APU_AREA_WINDOW_LO; // RW  32 bits
.CONST $APPS_SYS_APU_AREA_WINDOW_HI          0xFFFF9AE0; // RW  32 bits
.CONST $_APPS_SYS_APU_AREA_WINDOW_HI         $APPS_SYS_APU_AREA_WINDOW_HI; // RW  32 bits
.CONST $APPS_SYS_APU_MUTEX_LOCK              0xFFFF9AE4; // RW   4 bits
.CONST $_APPS_SYS_APU_MUTEX_LOCK             $APPS_SYS_APU_MUTEX_LOCK; // RW   4 bits
.CONST $APPS_SYS_APU_ACCESS_CTRL             0xFFFF9AE8; // RW   4 bits
.CONST $_APPS_SYS_APU_ACCESS_CTRL            $APPS_SYS_APU_ACCESS_CTRL; // RW   4 bits
.CONST $CLKGEN_MUTEX_LOCK                    0xFFFF9B08; // RW   4 bits
.CONST $_CLKGEN_MUTEX_LOCK                   $CLKGEN_MUTEX_LOCK; // RW   4 bits
.CONST $CLKGEN_ACCESS_CTRL                   0xFFFF9B0C; // RW   4 bits
.CONST $_CLKGEN_ACCESS_CTRL                  $CLKGEN_ACCESS_CTRL; // RW   4 bits
.CONST $APPS_SYS_SQIF_WINDOWS_MUTEX_LOCK     0xFFFF9B18; // RW   4 bits
.CONST $_APPS_SYS_SQIF_WINDOWS_MUTEX_LOCK    $APPS_SYS_SQIF_WINDOWS_MUTEX_LOCK; // RW   4 bits
.CONST $APPS_SYS_SQIF_WINDOWS_ACCESS_CTRL    0xFFFF9B1C; // RW   4 bits
.CONST $_APPS_SYS_SQIF_WINDOWS_ACCESS_CTRL   $APPS_SYS_SQIF_WINDOWS_ACCESS_CTRL; // RW   4 bits
.CONST $P0_TO_P1_INTERPROC_EVENT_1           0xFFFF9B20; //  W   1 bits
.CONST $_P0_TO_P1_INTERPROC_EVENT_1          $P0_TO_P1_INTERPROC_EVENT_1; //  W   1 bits
.CONST $P0_TO_P1_INTERPROC_EVENT_2           0xFFFF9B24; //  W   1 bits
.CONST $_P0_TO_P1_INTERPROC_EVENT_2          $P0_TO_P1_INTERPROC_EVENT_2; //  W   1 bits
.CONST $P1_TO_P0_INTERPROC_EVENT_1           0xFFFF9B28; //  W   1 bits
.CONST $_P1_TO_P0_INTERPROC_EVENT_1          $P1_TO_P0_INTERPROC_EVENT_1; //  W   1 bits
.CONST $P1_TO_P0_INTERPROC_EVENT_2           0xFFFF9B2C; //  W   1 bits
.CONST $_P1_TO_P0_INTERPROC_EVENT_2          $P1_TO_P0_INTERPROC_EVENT_2; //  W   1 bits
.CONST $APPS_SYS_CACHE_SEL                   0xFFFF9B30; // RW   1 bits
.CONST $_APPS_SYS_CACHE_SEL                  $APPS_SYS_CACHE_SEL; // RW   1 bits
.CONST $APPS_SYS_SQIF_SEL                    0xFFFF9B34; // RW   1 bits
.CONST $_APPS_SYS_SQIF_SEL                   $APPS_SYS_SQIF_SEL; // RW   1 bits
.CONST $APPS_SYS_SQIF_WINDOW_CONTROL         0xFFFF9B38; // RW   5 bits
.CONST $_APPS_SYS_SQIF_WINDOW_CONTROL        $APPS_SYS_SQIF_WINDOW_CONTROL; // RW   5 bits
.CONST $APPS_SYS_SQIF_WINDOW_OFFSET          0xFFFF9B3C; // RW  32 bits
.CONST $_APPS_SYS_SQIF_WINDOW_OFFSET         $APPS_SYS_SQIF_WINDOW_OFFSET; // RW  32 bits
.CONST $KALIMBA_PIO_INT_PIO1_EVENT_RISING_ENABLE 0xFFFF9C00; // RW  72 bits
.CONST $_KALIMBA_PIO_INT_PIO1_EVENT_RISING_ENABLE $KALIMBA_PIO_INT_PIO1_EVENT_RISING_ENABLE; // RW  72 bits
.CONST $KALIMBA_PIO_INT_PIO1_EVENT_RISING_ENABLE_WORD0 0xFFFF9C00; // RW 
.CONST $_KALIMBA_PIO_INT_PIO1_EVENT_RISING_ENABLE_WORD0 $KALIMBA_PIO_INT_PIO1_EVENT_RISING_ENABLE_WORD0; // RW 
.CONST $KALIMBA_PIO_INT_PIO1_EVENT_RISING_ENABLE_WORD1 0xFFFF9C04; // RW 
.CONST $_KALIMBA_PIO_INT_PIO1_EVENT_RISING_ENABLE_WORD1 $KALIMBA_PIO_INT_PIO1_EVENT_RISING_ENABLE_WORD1; // RW 
.CONST $KALIMBA_PIO_INT_PIO1_EVENT_RISING_ENABLE_WORD2 0xFFFF9C08; // RW 
.CONST $_KALIMBA_PIO_INT_PIO1_EVENT_RISING_ENABLE_WORD2 $KALIMBA_PIO_INT_PIO1_EVENT_RISING_ENABLE_WORD2; // RW 
.CONST $KALIMBA_PIO_INT_PIO1_EVENT_FALLING_ENABLE 0xFFFF9C18; // RW  72 bits
.CONST $_KALIMBA_PIO_INT_PIO1_EVENT_FALLING_ENABLE $KALIMBA_PIO_INT_PIO1_EVENT_FALLING_ENABLE; // RW  72 bits
.CONST $KALIMBA_PIO_INT_PIO1_EVENT_FALLING_ENABLE_WORD0 0xFFFF9C18; // RW 
.CONST $_KALIMBA_PIO_INT_PIO1_EVENT_FALLING_ENABLE_WORD0 $KALIMBA_PIO_INT_PIO1_EVENT_FALLING_ENABLE_WORD0; // RW 
.CONST $KALIMBA_PIO_INT_PIO1_EVENT_FALLING_ENABLE_WORD1 0xFFFF9C1C; // RW 
.CONST $_KALIMBA_PIO_INT_PIO1_EVENT_FALLING_ENABLE_WORD1 $KALIMBA_PIO_INT_PIO1_EVENT_FALLING_ENABLE_WORD1; // RW 
.CONST $KALIMBA_PIO_INT_PIO1_EVENT_FALLING_ENABLE_WORD2 0xFFFF9C20; // RW 
.CONST $_KALIMBA_PIO_INT_PIO1_EVENT_FALLING_ENABLE_WORD2 $KALIMBA_PIO_INT_PIO1_EVENT_FALLING_ENABLE_WORD2; // RW 
.CONST $KALIMBA_PIO_INT_PIO2_EVENT_RISING_ENABLE 0xFFFF9C30; // RW  72 bits
.CONST $_KALIMBA_PIO_INT_PIO2_EVENT_RISING_ENABLE $KALIMBA_PIO_INT_PIO2_EVENT_RISING_ENABLE; // RW  72 bits
.CONST $KALIMBA_PIO_INT_PIO2_EVENT_RISING_ENABLE_WORD0 0xFFFF9C30; // RW 
.CONST $_KALIMBA_PIO_INT_PIO2_EVENT_RISING_ENABLE_WORD0 $KALIMBA_PIO_INT_PIO2_EVENT_RISING_ENABLE_WORD0; // RW 
.CONST $KALIMBA_PIO_INT_PIO2_EVENT_RISING_ENABLE_WORD1 0xFFFF9C34; // RW 
.CONST $_KALIMBA_PIO_INT_PIO2_EVENT_RISING_ENABLE_WORD1 $KALIMBA_PIO_INT_PIO2_EVENT_RISING_ENABLE_WORD1; // RW 
.CONST $KALIMBA_PIO_INT_PIO2_EVENT_RISING_ENABLE_WORD2 0xFFFF9C38; // RW 
.CONST $_KALIMBA_PIO_INT_PIO2_EVENT_RISING_ENABLE_WORD2 $KALIMBA_PIO_INT_PIO2_EVENT_RISING_ENABLE_WORD2; // RW 
.CONST $KALIMBA_PIO_INT_PIO2_EVENT_FALLING_ENABLE 0xFFFF9C48; // RW  72 bits
.CONST $_KALIMBA_PIO_INT_PIO2_EVENT_FALLING_ENABLE $KALIMBA_PIO_INT_PIO2_EVENT_FALLING_ENABLE; // RW  72 bits
.CONST $KALIMBA_PIO_INT_PIO2_EVENT_FALLING_ENABLE_WORD0 0xFFFF9C48; // RW 
.CONST $_KALIMBA_PIO_INT_PIO2_EVENT_FALLING_ENABLE_WORD0 $KALIMBA_PIO_INT_PIO2_EVENT_FALLING_ENABLE_WORD0; // RW 
.CONST $KALIMBA_PIO_INT_PIO2_EVENT_FALLING_ENABLE_WORD1 0xFFFF9C4C; // RW 
.CONST $_KALIMBA_PIO_INT_PIO2_EVENT_FALLING_ENABLE_WORD1 $KALIMBA_PIO_INT_PIO2_EVENT_FALLING_ENABLE_WORD1; // RW 
.CONST $KALIMBA_PIO_INT_PIO2_EVENT_FALLING_ENABLE_WORD2 0xFFFF9C50; // RW 
.CONST $_KALIMBA_PIO_INT_PIO2_EVENT_FALLING_ENABLE_WORD2 $KALIMBA_PIO_INT_PIO2_EVENT_FALLING_ENABLE_WORD2; // RW 
.CONST $KALIMBA_PIO_INT_PIO1_EVENT_CAUSE     0xFFFF9C60; //  R  72 bits
.CONST $_KALIMBA_PIO_INT_PIO1_EVENT_CAUSE    $KALIMBA_PIO_INT_PIO1_EVENT_CAUSE; //  R  72 bits
.CONST $KALIMBA_PIO_INT_PIO1_EVENT_CAUSE_WORD0 0xFFFF9C60; //  R 
.CONST $_KALIMBA_PIO_INT_PIO1_EVENT_CAUSE_WORD0 $KALIMBA_PIO_INT_PIO1_EVENT_CAUSE_WORD0; //  R 
.CONST $KALIMBA_PIO_INT_PIO1_EVENT_CAUSE_WORD1 0xFFFF9C64; //  R 
.CONST $_KALIMBA_PIO_INT_PIO1_EVENT_CAUSE_WORD1 $KALIMBA_PIO_INT_PIO1_EVENT_CAUSE_WORD1; //  R 
.CONST $KALIMBA_PIO_INT_PIO1_EVENT_CAUSE_WORD2 0xFFFF9C68; //  R 
.CONST $_KALIMBA_PIO_INT_PIO1_EVENT_CAUSE_WORD2 $KALIMBA_PIO_INT_PIO1_EVENT_CAUSE_WORD2; //  R 
.CONST $KALIMBA_PIO_INT_PIO2_EVENT_CAUSE     0xFFFF9C78; //  R  72 bits
.CONST $_KALIMBA_PIO_INT_PIO2_EVENT_CAUSE    $KALIMBA_PIO_INT_PIO2_EVENT_CAUSE; //  R  72 bits
.CONST $KALIMBA_PIO_INT_PIO2_EVENT_CAUSE_WORD0 0xFFFF9C78; //  R 
.CONST $_KALIMBA_PIO_INT_PIO2_EVENT_CAUSE_WORD0 $KALIMBA_PIO_INT_PIO2_EVENT_CAUSE_WORD0; //  R 
.CONST $KALIMBA_PIO_INT_PIO2_EVENT_CAUSE_WORD1 0xFFFF9C7C; //  R 
.CONST $_KALIMBA_PIO_INT_PIO2_EVENT_CAUSE_WORD1 $KALIMBA_PIO_INT_PIO2_EVENT_CAUSE_WORD1; //  R 
.CONST $KALIMBA_PIO_INT_PIO2_EVENT_CAUSE_WORD2 0xFFFF9C80; //  R 
.CONST $_KALIMBA_PIO_INT_PIO2_EVENT_CAUSE_WORD2 $KALIMBA_PIO_INT_PIO2_EVENT_CAUSE_WORD2; //  R 
.CONST $KALIMBA_PIO_INT_PIO1_EVENT_CAUSE_CLEAR_DATA 0xFFFF9C90; // RW  72 bits
.CONST $_KALIMBA_PIO_INT_PIO1_EVENT_CAUSE_CLEAR_DATA $KALIMBA_PIO_INT_PIO1_EVENT_CAUSE_CLEAR_DATA; // RW  72 bits
.CONST $KALIMBA_PIO_INT_PIO1_EVENT_CAUSE_CLEAR_DATA_WORD0 0xFFFF9C90; // RW 
.CONST $_KALIMBA_PIO_INT_PIO1_EVENT_CAUSE_CLEAR_DATA_WORD0 $KALIMBA_PIO_INT_PIO1_EVENT_CAUSE_CLEAR_DATA_WORD0; // RW 
.CONST $KALIMBA_PIO_INT_PIO1_EVENT_CAUSE_CLEAR_DATA_WORD1 0xFFFF9C94; // RW 
.CONST $_KALIMBA_PIO_INT_PIO1_EVENT_CAUSE_CLEAR_DATA_WORD1 $KALIMBA_PIO_INT_PIO1_EVENT_CAUSE_CLEAR_DATA_WORD1; // RW 
.CONST $KALIMBA_PIO_INT_PIO1_EVENT_CAUSE_CLEAR_DATA_WORD2 0xFFFF9C98; // RW 
.CONST $_KALIMBA_PIO_INT_PIO1_EVENT_CAUSE_CLEAR_DATA_WORD2 $KALIMBA_PIO_INT_PIO1_EVENT_CAUSE_CLEAR_DATA_WORD2; // RW 
.CONST $KALIMBA_PIO_INT_PIO2_EVENT_CAUSE_CLEAR_DATA 0xFFFF9CA4; // RW  72 bits
.CONST $_KALIMBA_PIO_INT_PIO2_EVENT_CAUSE_CLEAR_DATA $KALIMBA_PIO_INT_PIO2_EVENT_CAUSE_CLEAR_DATA; // RW  72 bits
.CONST $KALIMBA_PIO_INT_PIO2_EVENT_CAUSE_CLEAR_DATA_WORD0 0xFFFF9CA4; // RW 
.CONST $_KALIMBA_PIO_INT_PIO2_EVENT_CAUSE_CLEAR_DATA_WORD0 $KALIMBA_PIO_INT_PIO2_EVENT_CAUSE_CLEAR_DATA_WORD0; // RW 
.CONST $KALIMBA_PIO_INT_PIO2_EVENT_CAUSE_CLEAR_DATA_WORD1 0xFFFF9CA8; // RW 
.CONST $_KALIMBA_PIO_INT_PIO2_EVENT_CAUSE_CLEAR_DATA_WORD1 $KALIMBA_PIO_INT_PIO2_EVENT_CAUSE_CLEAR_DATA_WORD1; // RW 
.CONST $KALIMBA_PIO_INT_PIO2_EVENT_CAUSE_CLEAR_DATA_WORD2 0xFFFF9CAC; // RW 
.CONST $_KALIMBA_PIO_INT_PIO2_EVENT_CAUSE_CLEAR_DATA_WORD2 $KALIMBA_PIO_INT_PIO2_EVENT_CAUSE_CLEAR_DATA_WORD2; // RW 
.CONST $KALIMBA_PIO_INT_TIMER_ENABLES        0xFFFF9D00; // RW  14 bits
.CONST $_KALIMBA_PIO_INT_TIMER_ENABLES       $KALIMBA_PIO_INT_TIMER_ENABLES; // RW  14 bits
.CONST $KALIMBA_PIO_INT_TIMER_PIO1_EVENT_PERIOD 0xFFFF9D04; // RW  16 bits
.CONST $_KALIMBA_PIO_INT_TIMER_PIO1_EVENT_PERIOD $KALIMBA_PIO_INT_TIMER_PIO1_EVENT_PERIOD; // RW  16 bits
.CONST $KALIMBA_PIO_INT_TIMER_PIO1_EVENT_TIME 0xFFFF9D08; // RW  32 bits
.CONST $_KALIMBA_PIO_INT_TIMER_PIO1_EVENT_TIME $KALIMBA_PIO_INT_TIMER_PIO1_EVENT_TIME; // RW  32 bits
.CONST $KALIMBA_PIO_INT_TIMER_PIO2_EVENT_PERIOD 0xFFFF9D10; // RW  16 bits
.CONST $_KALIMBA_PIO_INT_TIMER_PIO2_EVENT_PERIOD $KALIMBA_PIO_INT_TIMER_PIO2_EVENT_PERIOD; // RW  16 bits
.CONST $KALIMBA_PIO_INT_TIMER_PIO2_EVENT_TIME 0xFFFF9D14; // RW  32 bits
.CONST $_KALIMBA_PIO_INT_TIMER_PIO2_EVENT_TIME $KALIMBA_PIO_INT_TIMER_PIO2_EVENT_TIME; // RW  32 bits
.CONST $KALIMBA_PIO_INT_TIMER_SW3_EVENT_TIME 0xFFFF9D2C; // RW  32 bits
.CONST $_KALIMBA_PIO_INT_TIMER_SW3_EVENT_TIME $KALIMBA_PIO_INT_TIMER_SW3_EVENT_TIME; // RW  32 bits
.CONST $KALIMBA_PIO_INT_TIMER_TIME2          0xFFFF9D34; //  R  32 bits
.CONST $_KALIMBA_PIO_INT_TIMER_TIME2         $KALIMBA_PIO_INT_TIMER_TIME2; //  R  32 bits
.CONST $KALIMBA_PIO_INT_TIMER_PIO_STROBE_SELECT 0xFFFF9D3C; // RW  15 bits
.CONST $_KALIMBA_PIO_INT_TIMER_PIO_STROBE_SELECT $KALIMBA_PIO_INT_TIMER_PIO_STROBE_SELECT; // RW  15 bits
.CONST $KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_MASK 0xFFFF9D40; // RW  72 bits
.CONST $_KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_MASK $KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_MASK; // RW  72 bits
.CONST $KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_MASK_WORD0 0xFFFF9D40; // RW 
.CONST $_KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_MASK_WORD0 $KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_MASK_WORD0; // RW 
.CONST $KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_MASK_WORD1 0xFFFF9D44; // RW 
.CONST $_KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_MASK_WORD1 $KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_MASK_WORD1; // RW 
.CONST $KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_MASK_WORD2 0xFFFF9D48; // RW 
.CONST $_KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_MASK_WORD2 $KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_MASK_WORD2; // RW 
.CONST $KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_INVERT 0xFFFF9D58; // RW  72 bits
.CONST $_KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_INVERT $KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_INVERT; // RW  72 bits
.CONST $KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_INVERT_WORD0 0xFFFF9D58; // RW 
.CONST $_KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_INVERT_WORD0 $KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_INVERT_WORD0; // RW 
.CONST $KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_INVERT_WORD1 0xFFFF9D5C; // RW 
.CONST $_KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_INVERT_WORD1 $KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_INVERT_WORD1; // RW 
.CONST $KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_INVERT_WORD2 0xFFFF9D60; // RW 
.CONST $_KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_INVERT_WORD2 $KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_INVERT_WORD2; // RW 
.CONST $KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_STATUS 0xFFFF9D70; //  R  72 bits
.CONST $_KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_STATUS $KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_STATUS; //  R  72 bits
.CONST $KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_STATUS_WORD0 0xFFFF9D70; //  R 
.CONST $_KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_STATUS_WORD0 $KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_STATUS_WORD0; //  R 
.CONST $KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_STATUS_WORD1 0xFFFF9D74; //  R 
.CONST $_KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_STATUS_WORD1 $KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_STATUS_WORD1; //  R 
.CONST $KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_STATUS_WORD2 0xFFFF9D78; //  R 
.CONST $_KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_STATUS_WORD2 $KALIMBA_PIO_INT_TIMER_SW3_EVENT_PIO_STATUS_WORD2; //  R 
.CONST $KALIMBA_PIO_INT_TIMER_PIO1_EVENT_TIME_FINE 0xFFFF9D8C; // RW   7 bits
.CONST $_KALIMBA_PIO_INT_TIMER_PIO1_EVENT_TIME_FINE $KALIMBA_PIO_INT_TIMER_PIO1_EVENT_TIME_FINE; // RW   7 bits
.CONST $KALIMBA_PIO_INT_TIMER_PIO2_EVENT_TIME_FINE 0xFFFF9D90; // RW   7 bits
.CONST $_KALIMBA_PIO_INT_TIMER_PIO2_EVENT_TIME_FINE $KALIMBA_PIO_INT_TIMER_PIO2_EVENT_TIME_FINE; // RW   7 bits
.CONST $KALIMBA_PIO_INT_TIMER_PIO1_EVENT_PERIOD_FINE 0xFFFF9D94; // RW   7 bits
.CONST $_KALIMBA_PIO_INT_TIMER_PIO1_EVENT_PERIOD_FINE $KALIMBA_PIO_INT_TIMER_PIO1_EVENT_PERIOD_FINE; // RW   7 bits
.CONST $KALIMBA_PIO_INT_TIMER_PIO2_EVENT_PERIOD_FINE 0xFFFF9D98; // RW   7 bits
.CONST $_KALIMBA_PIO_INT_TIMER_PIO2_EVENT_PERIOD_FINE $KALIMBA_PIO_INT_TIMER_PIO2_EVENT_PERIOD_FINE; // RW   7 bits
.CONST $KALIMBA_PIO_INT_TIMER_PIO_STROBE1_TIME 0xFFFF9D9C; //  R  32 bits
.CONST $_KALIMBA_PIO_INT_TIMER_PIO_STROBE1_TIME $KALIMBA_PIO_INT_TIMER_PIO_STROBE1_TIME; //  R  32 bits
.CONST $KALIMBA_PIO_INT_TIMER_PIO_STROBE1_TIME_FINE 0xFFFF9DA4; //  R   7 bits
.CONST $_KALIMBA_PIO_INT_TIMER_PIO_STROBE1_TIME_FINE $KALIMBA_PIO_INT_TIMER_PIO_STROBE1_TIME_FINE; //  R   7 bits
.CONST $KALIMBA_PIO_INT_TIMER_PIO_STROBE2_TIME 0xFFFF9DA8; //  R  32 bits
.CONST $_KALIMBA_PIO_INT_TIMER_PIO_STROBE2_TIME $KALIMBA_PIO_INT_TIMER_PIO_STROBE2_TIME; //  R  32 bits
.CONST $KALIMBA_PIO_INT_TIMER_PIO_STROBE2_TIME_FINE 0xFFFF9DB0; //  R   7 bits
.CONST $_KALIMBA_PIO_INT_TIMER_PIO_STROBE2_TIME_FINE $KALIMBA_PIO_INT_TIMER_PIO_STROBE2_TIME_FINE; //  R   7 bits
.CONST $KALIMBA_PIO_INT_MUTEX_LOCK           0xFFFF9DB4; // RW   4 bits
.CONST $_KALIMBA_PIO_INT_MUTEX_LOCK          $KALIMBA_PIO_INT_MUTEX_LOCK; // RW   4 bits
.CONST $KALIMBA_PIO_INT_ACCESS_CTRL          0xFFFF9DB8; // RW   4 bits
.CONST $_KALIMBA_PIO_INT_ACCESS_CTRL         $KALIMBA_PIO_INT_ACCESS_CTRL; // RW   4 bits
.CONST $KALIMBA_PIO_INT_TIMER_PIO1_EVENT_SEL 0xFFFF9DBC; // RW   7 bits
.CONST $_KALIMBA_PIO_INT_TIMER_PIO1_EVENT_SEL $KALIMBA_PIO_INT_TIMER_PIO1_EVENT_SEL; // RW   7 bits
.CONST $KALIMBA_PIO_INT_TIMER_PIO2_EVENT_SEL 0xFFFF9DC0; // RW   7 bits
.CONST $_KALIMBA_PIO_INT_TIMER_PIO2_EVENT_SEL $KALIMBA_PIO_INT_TIMER_PIO2_EVENT_SEL; // RW   7 bits
.CONST $KALIMBA_READ_CACHE_CONTROL           0xFFFFA000; // RW   7 bits
.CONST $_KALIMBA_READ_CACHE_CONTROL          $KALIMBA_READ_CACHE_CONTROL; // RW   7 bits
.CONST $KALIMBA_READ_CACHE_PM_CONFIG         0xFFFFA004; // RW   3 bits
.CONST $_KALIMBA_READ_CACHE_PM_CONFIG        $KALIMBA_READ_CACHE_PM_CONFIG; // RW   3 bits
.CONST $KALIMBA_READ_CACHE_DM_CONFIG         0xFFFFA008; // RW   3 bits
.CONST $_KALIMBA_READ_CACHE_DM_CONFIG        $KALIMBA_READ_CACHE_DM_CONFIG; // RW   3 bits
.CONST $KALIMBA_READ_CACHE_PM_HIT_COUNTER    0xFFFFA00C; // RW  32 bits
.CONST $_KALIMBA_READ_CACHE_PM_HIT_COUNTER   $KALIMBA_READ_CACHE_PM_HIT_COUNTER; // RW  32 bits
.CONST $KALIMBA_READ_CACHE_PM_MISS_COUNTER   0xFFFFA010; // RW  32 bits
.CONST $_KALIMBA_READ_CACHE_PM_MISS_COUNTER  $KALIMBA_READ_CACHE_PM_MISS_COUNTER; // RW  32 bits
.CONST $KALIMBA_READ_CACHE_DM_HIT_COUNTER    0xFFFFA014; // RW  32 bits
.CONST $_KALIMBA_READ_CACHE_DM_HIT_COUNTER   $KALIMBA_READ_CACHE_DM_HIT_COUNTER; // RW  32 bits
.CONST $KALIMBA_READ_CACHE_DM_MISS_COUNTER   0xFFFFA018; // RW  32 bits
.CONST $_KALIMBA_READ_CACHE_DM_MISS_COUNTER  $KALIMBA_READ_CACHE_DM_MISS_COUNTER; // RW  32 bits
.CONST $KALIMBA_READ_CACHE_SLAVE_WAIT_COUNTER 0xFFFFA01C; // RW  32 bits
.CONST $_KALIMBA_READ_CACHE_SLAVE_WAIT_COUNTER $KALIMBA_READ_CACHE_SLAVE_WAIT_COUNTER; // RW  32 bits
.CONST $KALIMBA_READ_CACHE_INVALIDATE_CONTROL 0xFFFFA020; // RW   2 bits
.CONST $_KALIMBA_READ_CACHE_INVALIDATE_CONTROL $KALIMBA_READ_CACHE_INVALIDATE_CONTROL; // RW   2 bits
.CONST $KALIMBA_READ_CACHE_INVALIDATE_START_LINE 0xFFFFA024; // RW  16 bits
.CONST $_KALIMBA_READ_CACHE_INVALIDATE_START_LINE $KALIMBA_READ_CACHE_INVALIDATE_START_LINE; // RW  16 bits
.CONST $KALIMBA_READ_CACHE_INVALIDATE_NUM_LINES 0xFFFFA028; // RW  16 bits
.CONST $_KALIMBA_READ_CACHE_INVALIDATE_NUM_LINES $KALIMBA_READ_CACHE_INVALIDATE_NUM_LINES; // RW  16 bits
.CONST $KALIMBA_READ_CACHE_MISS_LOG_ENABLE   0xFFFFA02C; // RW   1 bits
.CONST $_KALIMBA_READ_CACHE_MISS_LOG_ENABLE  $KALIMBA_READ_CACHE_MISS_LOG_ENABLE; // RW   1 bits
.CONST $KALIMBA_READ_CACHE_MISS_LOG_BASE_ADDR 0xFFFFA030; // RW  32 bits
.CONST $_KALIMBA_READ_CACHE_MISS_LOG_BASE_ADDR $KALIMBA_READ_CACHE_MISS_LOG_BASE_ADDR; // RW  32 bits
.CONST $KALIMBA_READ_CACHE_MISS_LOG_SIZE     0xFFFFA034; // RW  16 bits
.CONST $_KALIMBA_READ_CACHE_MISS_LOG_SIZE    $KALIMBA_READ_CACHE_MISS_LOG_SIZE; // RW  16 bits
.CONST $KALIMBA_READ_CACHE_MISS_LOG_INDEX    0xFFFFA038; // RW  16 bits
.CONST $_KALIMBA_READ_CACHE_MISS_LOG_INDEX   $KALIMBA_READ_CACHE_MISS_LOG_INDEX; // RW  16 bits
.CONST $KALIMBA_READ_CACHE_PARAMS            0xFFFFA03C; //  R  32 bits
.CONST $_KALIMBA_READ_CACHE_PARAMS           $KALIMBA_READ_CACHE_PARAMS; //  R  32 bits
.CONST $KALIMBA_READ_CACHE_SOFT_RESET        0xFFFFA040; //  W   1 bits
.CONST $_KALIMBA_READ_CACHE_SOFT_RESET       $KALIMBA_READ_CACHE_SOFT_RESET; //  W   1 bits
.CONST $KALIMBA_READ_CACHE_DEBUG_EN          0xFFFFA044; //  W   1 bits
.CONST $_KALIMBA_READ_CACHE_DEBUG_EN         $KALIMBA_READ_CACHE_DEBUG_EN; //  W   1 bits
.CONST $KALIMBA_READ_CACHE_DEBUG_DATA        0xFFFFA048; //  R  32 bits
.CONST $_KALIMBA_READ_CACHE_DEBUG_DATA       $KALIMBA_READ_CACHE_DEBUG_DATA; //  R  32 bits
.CONST $KALIMBA_READ_CACHE_MUTEX_LOCK        0xFFFFA04C; // RW   4 bits
.CONST $_KALIMBA_READ_CACHE_MUTEX_LOCK       $KALIMBA_READ_CACHE_MUTEX_LOCK; // RW   4 bits
.CONST $KALIMBA_READ_CACHE_ACCESS_CTRL       0xFFFFA050; // RW   4 bits
.CONST $_KALIMBA_READ_CACHE_ACCESS_CTRL      $KALIMBA_READ_CACHE_ACCESS_CTRL; // RW   4 bits
.CONST $KALIMBA_READ_CACHE_TRANSITION_STATUS 0xFFFFA054; //  R   4 bits
.CONST $_KALIMBA_READ_CACHE_TRANSITION_STATUS $KALIMBA_READ_CACHE_TRANSITION_STATUS; //  R   4 bits
.CONST $KALIMBA_READ_CACHE_MASTER_WAIT_COUNTER_DM 0xFFFFA060; // RW  32 bits
.CONST $_KALIMBA_READ_CACHE_MASTER_WAIT_COUNTER_DM $KALIMBA_READ_CACHE_MASTER_WAIT_COUNTER_DM; // RW  32 bits
.CONST $KALIMBA_READ_CACHE_MASTER_WAIT_COUNTER_PM 0xFFFFA064; // RW  32 bits
.CONST $_KALIMBA_READ_CACHE_MASTER_WAIT_COUNTER_PM $KALIMBA_READ_CACHE_MASTER_WAIT_COUNTER_PM; // RW  32 bits
.CONST $KALIMBA_READ_CACHE_SLAVE_WAIT_COUNTER_DM 0xFFFFA068; // RW  32 bits
.CONST $_KALIMBA_READ_CACHE_SLAVE_WAIT_COUNTER_DM $KALIMBA_READ_CACHE_SLAVE_WAIT_COUNTER_DM; // RW  32 bits
.CONST $KALIMBA_READ_CACHE_SLAVE_WAIT_COUNTER_PM 0xFFFFA06C; // RW  32 bits
.CONST $_KALIMBA_READ_CACHE_SLAVE_WAIT_COUNTER_PM $KALIMBA_READ_CACHE_SLAVE_WAIT_COUNTER_PM; // RW  32 bits
.CONST $DM_BREAK0_START_ADDR                 0xFFFFFE00; // RW  32 bits
.CONST $_DM_BREAK0_START_ADDR                $DM_BREAK0_START_ADDR; // RW  32 bits
.CONST $DM_BREAK0_END_ADDR                   0xFFFFFE04; // RW  32 bits
.CONST $_DM_BREAK0_END_ADDR                  $DM_BREAK0_END_ADDR; // RW  32 bits
.CONST $DM_BREAK1_START_ADDR                 0xFFFFFE08; // RW  32 bits
.CONST $_DM_BREAK1_START_ADDR                $DM_BREAK1_START_ADDR; // RW  32 bits
.CONST $DM_BREAK1_END_ADDR                   0xFFFFFE0C; // RW  32 bits
.CONST $_DM_BREAK1_END_ADDR                  $DM_BREAK1_END_ADDR; // RW  32 bits
.CONST $PM_BREAK0_ADDR                       0xFFFFFE10; // RW  32 bits
.CONST $_PM_BREAK0_ADDR                      $PM_BREAK0_ADDR; // RW  32 bits
.CONST $PM_BREAK1_ADDR                       0xFFFFFE14; // RW  32 bits
.CONST $_PM_BREAK1_ADDR                      $PM_BREAK1_ADDR; // RW  32 bits
.CONST $PM_BREAK2_ADDR                       0xFFFFFE18; // RW  32 bits
.CONST $_PM_BREAK2_ADDR                      $PM_BREAK2_ADDR; // RW  32 bits
.CONST $PM_BREAK3_ADDR                       0xFFFFFE1C; // RW  32 bits
.CONST $_PM_BREAK3_ADDR                      $PM_BREAK3_ADDR; // RW  32 bits
.CONST $PM_BREAK4_ADDR                       0xFFFFFE20; // RW  32 bits
.CONST $_PM_BREAK4_ADDR                      $PM_BREAK4_ADDR; // RW  32 bits
.CONST $PM_BREAK5_ADDR                       0xFFFFFE24; // RW  32 bits
.CONST $_PM_BREAK5_ADDR                      $PM_BREAK5_ADDR; // RW  32 bits
.CONST $PM_BREAK6_ADDR                       0xFFFFFE28; // RW  32 bits
.CONST $_PM_BREAK6_ADDR                      $PM_BREAK6_ADDR; // RW  32 bits
.CONST $PM_BREAK7_ADDR                       0xFFFFFE2C; // RW  32 bits
.CONST $_PM_BREAK7_ADDR                      $PM_BREAK7_ADDR; // RW  32 bits
.CONST $DEBUG                                0xFFFFFE30; // RW  19 bits
.CONST $_DEBUG                               $DEBUG; // RW  19 bits
.CONST $STATUS                               0xFFFFFE34; //  R  17 bits
.CONST $_STATUS                              $STATUS; //  R  17 bits
.CONST $EXTERNAL_BREAK                       0xFFFFFE38; // RW   2 bits
.CONST $_EXTERNAL_BREAK                      $EXTERNAL_BREAK; // RW   2 bits
.CONST $INTERPROC_BREAK                      0xFFFFFE3C; // RW   2 bits
.CONST $_INTERPROC_BREAK                     $INTERPROC_BREAK; // RW   2 bits
.CONST $DM_BREAK0_BYTE_SELECT                0xFFFFFE40; // RW   4 bits
.CONST $_DM_BREAK0_BYTE_SELECT               $DM_BREAK0_BYTE_SELECT; // RW   4 bits
.CONST $DM_BREAK0_DATA_VALUE                 0xFFFFFE44; // RW  32 bits
.CONST $_DM_BREAK0_DATA_VALUE                $DM_BREAK0_DATA_VALUE; // RW  32 bits
.CONST $DM_BREAK0_DATA_MASK                  0xFFFFFE48; // RW  32 bits
.CONST $_DM_BREAK0_DATA_MASK                 $DM_BREAK0_DATA_MASK; // RW  32 bits
.CONST $DM_BREAK1_BYTE_SELECT                0xFFFFFE4C; // RW   4 bits
.CONST $_DM_BREAK1_BYTE_SELECT               $DM_BREAK1_BYTE_SELECT; // RW   4 bits
.CONST $DM_BREAK1_DATA_VALUE                 0xFFFFFE50; // RW  32 bits
.CONST $_DM_BREAK1_DATA_VALUE                $DM_BREAK1_DATA_VALUE; // RW  32 bits
.CONST $DM_BREAK1_DATA_MASK                  0xFFFFFE54; // RW  32 bits
.CONST $_DM_BREAK1_DATA_MASK                 $DM_BREAK1_DATA_MASK; // RW  32 bits
.CONST $EXTERNAL_BREAK_STATUS                0xFFFFFE58; // RW   1 bits
.CONST $_EXTERNAL_BREAK_STATUS               $EXTERNAL_BREAK_STATUS; // RW   1 bits
.CONST $DEBUG_PM_BREAK7_ENABLES              0xFFFFFE5C; // RW   7 bits
.CONST $_DEBUG_PM_BREAK7_ENABLES             $DEBUG_PM_BREAK7_ENABLES; // RW   7 bits
.CONST $DEBUG_PM_BREAK7_ENABLED              0xFFFFFE60; // RW   7 bits
.CONST $_DEBUG_PM_BREAK7_ENABLED             $DEBUG_PM_BREAK7_ENABLED; // RW   7 bits
.CONST $REGFILE_PC                           0xFFFFFF00; // RW  32 bits
.CONST $_REGFILE_PC                          $REGFILE_PC; // RW  32 bits
.CONST $REGFILE_RMAC2                        0xFFFFFF04; // RW  32 bits
.CONST $_REGFILE_RMAC2                       $REGFILE_RMAC2; // RW  32 bits
.CONST $REGFILE_RMAC1                        0xFFFFFF08; // RW  32 bits
.CONST $_REGFILE_RMAC1                       $REGFILE_RMAC1; // RW  32 bits
.CONST $REGFILE_RMAC0                        0xFFFFFF0C; // RW  32 bits
.CONST $_REGFILE_RMAC0                       $REGFILE_RMAC0; // RW  32 bits
.CONST $REGFILE_RMAC24                       0xFFFFFF10; // RW  32 bits
.CONST $_REGFILE_RMAC24                      $REGFILE_RMAC24; // RW  32 bits
.CONST $REGFILE_R0                           0xFFFFFF14; // RW  32 bits
.CONST $_REGFILE_R0                          $REGFILE_R0; // RW  32 bits
.CONST $REGFILE_R1                           0xFFFFFF18; // RW  32 bits
.CONST $_REGFILE_R1                          $REGFILE_R1; // RW  32 bits
.CONST $REGFILE_R2                           0xFFFFFF1C; // RW  32 bits
.CONST $_REGFILE_R2                          $REGFILE_R2; // RW  32 bits
.CONST $REGFILE_R3                           0xFFFFFF20; // RW  32 bits
.CONST $_REGFILE_R3                          $REGFILE_R3; // RW  32 bits
.CONST $REGFILE_R4                           0xFFFFFF24; // RW  32 bits
.CONST $_REGFILE_R4                          $REGFILE_R4; // RW  32 bits
.CONST $REGFILE_R5                           0xFFFFFF28; // RW  32 bits
.CONST $_REGFILE_R5                          $REGFILE_R5; // RW  32 bits
.CONST $REGFILE_R6                           0xFFFFFF2C; // RW  32 bits
.CONST $_REGFILE_R6                          $REGFILE_R6; // RW  32 bits
.CONST $REGFILE_R7                           0xFFFFFF30; // RW  32 bits
.CONST $_REGFILE_R7                          $REGFILE_R7; // RW  32 bits
.CONST $REGFILE_R8                           0xFFFFFF34; // RW  32 bits
.CONST $_REGFILE_R8                          $REGFILE_R8; // RW  32 bits
.CONST $REGFILE_R9                           0xFFFFFF38; // RW  32 bits
.CONST $_REGFILE_R9                          $REGFILE_R9; // RW  32 bits
.CONST $REGFILE_R10                          0xFFFFFF3C; // RW  32 bits
.CONST $_REGFILE_R10                         $REGFILE_R10; // RW  32 bits
.CONST $REGFILE_RLINK                        0xFFFFFF40; // RW  32 bits
.CONST $_REGFILE_RLINK                       $REGFILE_RLINK; // RW  32 bits
.CONST $REGFILE_RFLAGS                       0xFFFFFF44; // RW  32 bits
.CONST $_REGFILE_RFLAGS                      $REGFILE_RFLAGS; // RW  32 bits
.CONST $REGFILE_RMACB24                      0xFFFFFF48; // RW  32 bits
.CONST $_REGFILE_RMACB24                     $REGFILE_RMACB24; // RW  32 bits
.CONST $REGFILE_I0                           0xFFFFFF4C; // RW  32 bits
.CONST $_REGFILE_I0                          $REGFILE_I0; // RW  32 bits
.CONST $REGFILE_I1                           0xFFFFFF50; // RW  32 bits
.CONST $_REGFILE_I1                          $REGFILE_I1; // RW  32 bits
.CONST $REGFILE_I2                           0xFFFFFF54; // RW  32 bits
.CONST $_REGFILE_I2                          $REGFILE_I2; // RW  32 bits
.CONST $REGFILE_I3                           0xFFFFFF58; // RW  32 bits
.CONST $_REGFILE_I3                          $REGFILE_I3; // RW  32 bits
.CONST $REGFILE_I4                           0xFFFFFF5C; // RW  32 bits
.CONST $_REGFILE_I4                          $REGFILE_I4; // RW  32 bits
.CONST $REGFILE_I5                           0xFFFFFF60; // RW  32 bits
.CONST $_REGFILE_I5                          $REGFILE_I5; // RW  32 bits
.CONST $REGFILE_I6                           0xFFFFFF64; // RW  32 bits
.CONST $_REGFILE_I6                          $REGFILE_I6; // RW  32 bits
.CONST $REGFILE_I7                           0xFFFFFF68; // RW  32 bits
.CONST $_REGFILE_I7                          $REGFILE_I7; // RW  32 bits
.CONST $REGFILE_M0                           0xFFFFFF6C; // RW  32 bits
.CONST $_REGFILE_M0                          $REGFILE_M0; // RW  32 bits
.CONST $REGFILE_M1                           0xFFFFFF70; // RW  32 bits
.CONST $_REGFILE_M1                          $REGFILE_M1; // RW  32 bits
.CONST $REGFILE_M2                           0xFFFFFF74; // RW  32 bits
.CONST $_REGFILE_M2                          $REGFILE_M2; // RW  32 bits
.CONST $REGFILE_M3                           0xFFFFFF78; // RW  32 bits
.CONST $_REGFILE_M3                          $REGFILE_M3; // RW  32 bits
.CONST $REGFILE_L0                           0xFFFFFF7C; // RW  32 bits
.CONST $_REGFILE_L0                          $REGFILE_L0; // RW  32 bits
.CONST $REGFILE_L1                           0xFFFFFF80; // RW  32 bits
.CONST $_REGFILE_L1                          $REGFILE_L1; // RW  32 bits
.CONST $REGFILE_L4                           0xFFFFFF84; // RW  32 bits
.CONST $_REGFILE_L4                          $REGFILE_L4; // RW  32 bits
.CONST $REGFILE_L5                           0xFFFFFF88; // RW  32 bits
.CONST $_REGFILE_L5                          $REGFILE_L5; // RW  32 bits
.CONST $REGFILE_NUM_RUNCLKS                  0xFFFFFF8C; //  R  32 bits
.CONST $_REGFILE_NUM_RUNCLKS                 $REGFILE_NUM_RUNCLKS; //  R  32 bits
.CONST $REGFILE_NUM_INSTRS                   0xFFFFFF90; //  R  32 bits
.CONST $_REGFILE_NUM_INSTRS                  $REGFILE_NUM_INSTRS; //  R  32 bits
.CONST $REGFILE_NUM_CORE_STALLS              0xFFFFFF94; //  R  32 bits
.CONST $_REGFILE_NUM_CORE_STALLS             $REGFILE_NUM_CORE_STALLS; //  R  32 bits
.CONST $REGFILE_RMACB2                       0xFFFFFF98; // RW  32 bits
.CONST $_REGFILE_RMACB2                      $REGFILE_RMACB2; // RW  32 bits
.CONST $REGFILE_RMACB1                       0xFFFFFF9C; // RW  32 bits
.CONST $_REGFILE_RMACB1                      $REGFILE_RMACB1; // RW  32 bits
.CONST $REGFILE_RMACB0                       0xFFFFFFA0; // RW  32 bits
.CONST $_REGFILE_RMACB0                      $REGFILE_RMACB0; // RW  32 bits
.CONST $REGFILE_B0                           0xFFFFFFA4; // RW  32 bits
.CONST $_REGFILE_B0                          $REGFILE_B0; // RW  32 bits
.CONST $REGFILE_B1                           0xFFFFFFA8; // RW  32 bits
.CONST $_REGFILE_B1                          $REGFILE_B1; // RW  32 bits
.CONST $REGFILE_B4                           0xFFFFFFAC; // RW  32 bits
.CONST $_REGFILE_B4                          $REGFILE_B4; // RW  32 bits
.CONST $REGFILE_B5                           0xFFFFFFB0; // RW  32 bits
.CONST $_REGFILE_B5                          $REGFILE_B5; // RW  32 bits
.CONST $REGFILE_FP                           0xFFFFFFB4; // RW  32 bits
.CONST $_REGFILE_FP                          $REGFILE_FP; // RW  32 bits
.CONST $REGFILE_SP                           0xFFFFFFB8; // RW  32 bits
.CONST $_REGFILE_SP                          $REGFILE_SP; // RW  32 bits
// -- Aliases --
.CONST $MMU_FREE_LIST_ADDR                   0xFFFF9A00; // RW  32 bits - aliased to reg VM_FREE_LIST_ADDR
.CONST $_MMU_FREE_LIST_ADDR                  $MMU_FREE_LIST_ADDR; // RW  32 bits
.CONST $MMU_FREE_LIST_NEXT_ADDR              0xFFFF9A50; //  R  32 bits - aliased to reg VM_FREE_LIST_NEXT_ADDR
.CONST $_MMU_FREE_LIST_NEXT_ADDR             $MMU_FREE_LIST_NEXT_ADDR; //  R  32 bits
.CONST $MMU_FREE_LIST_END_ADDR               0xFFFF9A04; // RW  32 bits - aliased to reg VM_FREE_LIST_END_ADDR
.CONST $_MMU_FREE_LIST_END_ADDR              $MMU_FREE_LIST_END_ADDR; // RW  32 bits
.CONST $MMU_FREE_LIST_ADD_PAGE               0xFFFF9A08; // RW  16 bits - aliased to reg VM_FREE_LIST_ADD_PAGE
.CONST $_MMU_FREE_LIST_ADD_PAGE              $MMU_FREE_LIST_ADD_PAGE; // RW  16 bits
.CONST $MMU_BUFFER_ACCESS_CPU0_HANDLE        0xFFFF9A54; // RW  12 bits - aliased to reg VM_BUFFER_ACCESS_CPU0_HANDLE
.CONST $_MMU_BUFFER_ACCESS_CPU0_HANDLE       $MMU_BUFFER_ACCESS_CPU0_HANDLE; // RW  12 bits
.CONST $MMU_BUFFER_ACCESS_CPU0_OFFSET_WRITE  0xFFFF9A58; // RW  18 bits - aliased to reg VM_BUFFER_ACCESS_CPU0_OFFSET_WRITE
.CONST $_MMU_BUFFER_ACCESS_CPU0_OFFSET_WRITE $MMU_BUFFER_ACCESS_CPU0_OFFSET_WRITE; // RW  18 bits
.CONST $MMU_BUFFER_ACCESS_CPU0_OFFSET_READ   0xFFFF9A64; //  R  18 bits - aliased to reg VM_BUFFER_ACCESS_CPU0_OFFSET_READ
.CONST $_MMU_BUFFER_ACCESS_CPU0_OFFSET_READ  $MMU_BUFFER_ACCESS_CPU0_OFFSET_READ; //  R  18 bits
.CONST $MMU_BUFFER_ACCESS_CPU0_DO_ACTION     0xFFFF9A5C; // RW   1 bits - aliased to reg VM_BUFFER_ACCESS_CPU0_DO_ACTION
.CONST $_MMU_BUFFER_ACCESS_CPU0_DO_ACTION    $MMU_BUFFER_ACCESS_CPU0_DO_ACTION; // RW   1 bits
.CONST $MMU_BUFFER_ACCESS_CPU0_STATUS        0xFFFF9A60; //  R   5 bits - aliased to reg VM_BUFFER_ACCESS_CPU0_STATUS
.CONST $_MMU_BUFFER_ACCESS_CPU0_STATUS       $MMU_BUFFER_ACCESS_CPU0_STATUS; //  R   5 bits
.CONST $MMU_BUFFER_ACCESS_CPU1_HANDLE        0xFFFF9A68; // RW  12 bits - aliased to reg VM_BUFFER_ACCESS_CPU1_HANDLE
.CONST $_MMU_BUFFER_ACCESS_CPU1_HANDLE       $MMU_BUFFER_ACCESS_CPU1_HANDLE; // RW  12 bits
.CONST $MMU_BUFFER_ACCESS_CPU1_OFFSET_WRITE  0xFFFF9A6C; // RW  18 bits - aliased to reg VM_BUFFER_ACCESS_CPU1_OFFSET_WRITE
.CONST $_MMU_BUFFER_ACCESS_CPU1_OFFSET_WRITE $MMU_BUFFER_ACCESS_CPU1_OFFSET_WRITE; // RW  18 bits
.CONST $MMU_BUFFER_ACCESS_CPU1_OFFSET_READ   0xFFFF9A78; //  R  18 bits - aliased to reg VM_BUFFER_ACCESS_CPU1_OFFSET_READ
.CONST $_MMU_BUFFER_ACCESS_CPU1_OFFSET_READ  $MMU_BUFFER_ACCESS_CPU1_OFFSET_READ; //  R  18 bits
.CONST $MMU_BUFFER_ACCESS_CPU1_DO_ACTION     0xFFFF9A70; // RW   1 bits - aliased to reg VM_BUFFER_ACCESS_CPU1_DO_ACTION
.CONST $_MMU_BUFFER_ACCESS_CPU1_DO_ACTION    $MMU_BUFFER_ACCESS_CPU1_DO_ACTION; // RW   1 bits
.CONST $MMU_BUFFER_ACCESS_CPU1_STATUS        0xFFFF9A74; //  R   5 bits - aliased to reg VM_BUFFER_ACCESS_CPU1_STATUS
.CONST $_MMU_BUFFER_ACCESS_CPU1_STATUS       $MMU_BUFFER_ACCESS_CPU1_STATUS; //  R   5 bits
// -- End --